Simulation Results: lc_ctrl/volatile_unlock_disabled

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.71 %
  • code
  • 88.83 %
  • assert
  • 96.25 %
  • func
  • 78.06 %
  • block
  • 95.80 %
  • line
  • 96.36 %
  • branch
  • 89.31 %
  • toggle
  • 79.18 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 233.057us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 17.317us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 12.881us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 222.061us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.071us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 27.652us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 12.881us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 242.797us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 13.519us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 393.431us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 5.000s 302.951us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 4.000s 198.017us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.000s 1469.644us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 59.903us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 177.627us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.000s 4968.541us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 112.361us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 140.057us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.000s 246.438us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 50.719us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 415.151us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 12.712us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.515s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 46.991us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 179.378us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 179.378us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 17.317us 1 1 100.00
lc_ctrl_csr_rw 1.000s 12.881us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.071us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 31.379us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 17.317us 1 1 100.00
lc_ctrl_csr_rw 1.000s 12.881us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 46.071us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 31.379us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.000s 251.250us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 396.006us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 396.006us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 242.797us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 251.250us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 251.250us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 251.250us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 251.250us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 251.250us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 251.250us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 251.250us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 251.250us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 393.431us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 1570.495us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1238.157us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1238.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 7394632657108974226843309904181455924906131941683645438289531694321545170313 None
lc_ctrl_state_post_trans 26237330707952974729844268464491088578729319205391170982109511852909418453780 None
lc_ctrl_prog_failure 67436318709906634409287121525750315789514316061916938400910288698587022098746 None
lc_ctrl_errors 54190397898507510212263599126606528935110397799031011366424267875286922257281 None
lc_ctrl_jtag_state_failure 111870838277367261456985656352161556156496425130285601104684758913288088348083 None
lc_ctrl_jtag_state_post_trans 35383920574946026307176001000948840861124248773587651594392298482860113525085 None
lc_ctrl_jtag_prog_failure 33615239023914460560946295318184319825330197812487889601042184748740294917372 None
lc_ctrl_jtag_errors 50627624868464732389607491113163744612188269306649818174045888894392316563838 None
lc_ctrl_sec_mubi 104419133262337308116704481128383215470593067596925491608069999578698100252814 None
lc_ctrl_stress_all 8755453494772190930052398745893987155238762134847652568041009844951010705611 None
lc_ctrl_stress_all_with_rand_reset 77473146139156025759862692125683604376864557297638623126827077627894492846588 None