Simulation Results: lc_ctrl/volatile_unlock_enabled

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.00 %
  • code
  • 89.96 %
  • assert
  • 95.97 %
  • func
  • 78.06 %
  • block
  • 96.30 %
  • line
  • 97.15 %
  • branch
  • 90.62 %
  • toggle
  • 79.21 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 42.615us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 26.395us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 14.560us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 61.897us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.586us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 19.207us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 14.560us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3601.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 245.562us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 22.714us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 1442.876us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 3.000s 259.461us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 8.000s 581.338us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.000s 2949.363us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 1475.144us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 271.119us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 605.053us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 152.340us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 72.081us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 257.334us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 219.686us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 193.815us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 16.497us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.101s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 176.705us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 54.041us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 54.041us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 26.395us 1 1 100.00
lc_ctrl_csr_rw 1.000s 14.560us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.586us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 156.123us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 26.395us 1 1 100.00
lc_ctrl_csr_rw 1.000s 14.560us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.586us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 156.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 221.224us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 119.457us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 119.457us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 245.562us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 221.224us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 221.224us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 221.224us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 221.224us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 221.224us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 221.224us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 221.224us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 221.224us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 1442.876us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3601.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 286.722us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.000s 2256.915us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.000s 2256.915us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 48722402520842712939553296942499640553506267334078860527792079020650469198331 None
lc_ctrl_state_post_trans 92607518701693737987209244286389660098711816611110718937910000358969197380090 None
lc_ctrl_prog_failure 105169723857869155774570170488509239772010927269106720226710405383417896308727 None
lc_ctrl_errors 68843053900514024591435458012596182548134656009523506085724319424934671561650 None
lc_ctrl_jtag_state_failure 19045336186381434590323081610064712404740790672232629487057112020302952026454 None
lc_ctrl_jtag_state_post_trans 66744043096445979655225173416160061141794527625542486694772519717248874643 None
lc_ctrl_jtag_prog_failure 106575243214653548433548599104883199440872029267756472371793371487144200359913 None
lc_ctrl_jtag_errors 109069701318672266307756773822388481225366701615071844829526865354574166945431 None
lc_ctrl_sec_mubi 96456112440259199312809842795798557085944653313697302127394140789452595633718 None
lc_ctrl_stress_all 28960312894580915767111519243553251982913915453971144085049220072868557897196 None
lc_ctrl_stress_all_with_rand_reset 49758186592696196032407564399733796139271296194855405466661918470621072716873 None