Simulation Results: mbx

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.15 %
  • code
  • 89.40 %
  • assert
  • 96.96 %
  • func
  • 75.10 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 79.59 %
Validation stages
V1
83.33%
V2
90.91%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 65.000s 18729.164us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 51.481us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 13.213us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 849.813us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 26.454us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 4.032us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 13.213us 1 1 100.00
mbx_csr_aliasing 2.000s 26.454us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 231.000s 101015.069us 1 1 100.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 134.000s 5967.687us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 38.000s 3611.516us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 13.000s 780.067us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 27.661us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 52.554us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 25.405us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 25.405us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 51.481us 1 1 100.00
mbx_csr_rw 1.000s 13.213us 1 1 100.00
mbx_csr_aliasing 2.000s 26.454us 1 1 100.00
mbx_same_csr_outstanding 2.000s 62.426us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 51.481us 1 1 100.00
mbx_csr_rw 1.000s 13.213us 1 1 100.00
mbx_csr_aliasing 2.000s 26.454us 1 1 100.00
mbx_same_csr_outstanding 2.000s 62.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 508.295us 1 1 100.00
mbx_sec_cm 1.000s 56.742us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:696) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 82120231083052450728295774994831345683776828523251121842582674682698246180532 85
TL item was: req: (cip_tl_seq_item@18418) { a_addr: 'hc29b7d30 a_data: 'h6e924ae7 a_mask: 'h1 a_size: 'h2 a_param: 'h0 a_source: 'h8c a_opcode: 'h1 a_user: 'h24d3a d_param: 'h0 d_source: 'h8c d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 25404527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 16593301922966030662631295434657982298397139105364315441999017325396424424123 86
TL item was: req: (cip_tl_seq_item@17658) { a_addr: 'h2b19b0f4 a_data: 'h9b0aeafd a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'he1 a_opcode: 'h1 a_user: 'h25b8c d_param: 'h0 d_source: 'he1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 4031863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---