Simulation Results: otbn

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.36 %
  • code
  • 86.13 %
  • assert
  • 90.06 %
  • func
  • 97.88 %
  • block
  • 99.24 %
  • line
  • 99.46 %
  • branch
  • 94.52 %
  • toggle
  • 84.33 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 14.000s 163.660us 1 1 100.00
otbn_smoke_vectorized 11.000s 23.257us 1 1 100.00
single_binary 1 1 100.00
otbn_single 28.000s 99.620us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 15.000s 62.848us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 15.121us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 8.000s 45.688us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 14.798us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 344.330us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 15.121us 1 1 100.00
otbn_csr_aliasing 5.000s 14.798us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 125.000s 2853.585us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 35.000s 2823.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 62.000s 110.016us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 78.000s 1614.925us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 76.000s 217.097us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 60.000s 146.731us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 12.000s 36.180us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 11.000s 18.358us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 13.000s 71.360us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 52.997us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 23.533us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 153.739us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 153.739us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 15.000s 62.848us 1 1 100.00
otbn_csr_rw 5.000s 15.121us 1 1 100.00
otbn_csr_aliasing 5.000s 14.798us 1 1 100.00
otbn_same_csr_outstanding 5.000s 55.878us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 15.000s 62.848us 1 1 100.00
otbn_csr_rw 5.000s 15.121us 1 1 100.00
otbn_csr_aliasing 5.000s 14.798us 1 1 100.00
otbn_same_csr_outstanding 5.000s 55.878us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 24.002us 1 1 100.00
otbn_dmem_err 14.000s 112.293us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 12.000s 80.825us 1 1 100.00
otbn_controller_ispr_rdata_err 12.000s 61.861us 1 1 100.00
otbn_mac_bignum_acc_err 13.000s 209.950us 1 1 100.00
otbn_urnd_err 12.000s 15.719us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 16.436us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 8.000s 39.858us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 8.000s 17.944us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
otbn_tl_intg_err 17.000s 72.500us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 44.000s 130.052us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 14.000s 163.660us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 14.000s 112.293us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 24.002us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 17.000s 72.500us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 12.000s 36.180us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 24.002us 1 1 100.00
otbn_dmem_err 14.000s 112.293us 1 1 100.00
otbn_zero_state_err_urnd 11.000s 18.358us 1 1 100.00
otbn_illegal_mem_acc 8.000s 16.436us 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 28.000s 99.620us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 24.002us 1 1 100.00
otbn_dmem_err 14.000s 112.293us 1 1 100.00
otbn_zero_state_err_urnd 11.000s 18.358us 1 1 100.00
otbn_illegal_mem_acc 8.000s 16.436us 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 12.000s 36.180us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 24.002us 1 1 100.00
otbn_dmem_err 14.000s 112.293us 1 1 100.00
otbn_zero_state_err_urnd 11.000s 18.358us 1 1 100.00
otbn_illegal_mem_acc 8.000s 16.436us 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 28.000s 99.620us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 9.000s 36.617us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 11.000s 23.859us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 42.000s 93.157us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 42.000s 93.157us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 50.877us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 12.000s 62.478us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 22.191us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 22.191us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 30.000s 191.400us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 28.000s 99.620us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 28.000s 99.620us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 28.000s 99.620us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 76.000s 217.097us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 28.000s 99.620us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 28.000s 99.620us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 13.000s 334.321us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 28.000s 99.620us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 288.000s 6810.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 454.000s 3035.195us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 71450310626213525446725372487363521960533351963727436334461597864554455625689 369
UVM_INFO @ 3035194686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 16358263312888451043677246088398013871419931108653583670939008273594177667637 111
UVM_ERROR @ 15718880 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 15718880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---