Simulation Results: otp_ctrl

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.50 %
  • code
  • 71.87 %
  • assert
  • 93.71 %
  • func
  • 51.92 %
  • line
  • 87.37 %
  • branch
  • 83.89 %
  • cond
  • 85.77 %
  • toggle
  • 65.85 %
  • FSM
  • 36.47 %
Validation stages
V1
100.00%
V2
65.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 3.020s 220.998us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 8.100s 232.599us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.390s 78.222us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.550s 50.086us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 12.830s 1242.764us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.000s 261.012us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.530s 150.035us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.550s 50.086us 1 1 100.00
otp_ctrl_csr_aliasing 3.000s 261.012us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.240s 42.230us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.230s 158.600us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 186.300s 31290.237us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.510s 547.943us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 8.950s 4197.588us 1 1 100.00
otp_ctrl_check_fail 6.610s 221.353us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.490s 145.773us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 23.530s 1402.241us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 11.030s 341.775us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 6.510s 518.700us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 5.580s 202.746us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 5.460s 291.809us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 20.370s 1081.657us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 13.880s 820.715us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.160s 86.155us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.930s 1154.167us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 8.900s 672.489us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 8.900s 672.489us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.390s 78.222us 1 1 100.00
otp_ctrl_csr_rw 2.550s 50.086us 1 1 100.00
otp_ctrl_csr_aliasing 3.000s 261.012us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.660s 68.073us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.390s 78.222us 1 1 100.00
otp_ctrl_csr_rw 2.550s 50.086us 1 1 100.00
otp_ctrl_csr_aliasing 3.000s 261.012us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.660s 68.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
otp_ctrl_tl_intg_err 30.760s 1532.465us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 30.760s 1532.465us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 8.100s 232.599us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 8.100s 232.599us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
otp_ctrl_macro_errs 5.460s 291.809us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
otp_ctrl_macro_errs 5.460s 291.809us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.000s 629.808us 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.510s 547.943us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 6.610s 221.353us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 23.530s 1402.241us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 23.530s 1402.241us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 23.530s 1402.241us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 23.530s 1402.241us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 23.530s 1402.241us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 8.100s 232.599us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 23.530s 1402.241us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 8.100s 232.599us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 441.350s 18483.521us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.490s 145.773us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 8.100s 232.599us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 8.100s 232.599us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 5.460s 291.809us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 107.040s 68849.395us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 24.570s 550.517us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_check_fail 12415476695961702052908162545108517930988300398669639441571965445496509617153 3002
UVM_INFO @ 221352681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 79514609653939327563454039648118311522219396904195205542676427538646365662220 10592
UVM_INFO @ 341775345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 7586089066137839110239344804469035179093180178413909603335536520296493999695 9958
UVM_INFO @ 1081656696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82122579038534323397795747771743341453781343014413727017550348283557141083846 11185
UVM_INFO @ 550516712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 66131998377971226400217337358048546308698800611280229992425271746559779409928 110263
UVM_INFO @ 31290237283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 19282147007251398249629332295099032965966509380778233269401237001888783252936 95
UVM_INFO @ 68849395293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_dai_errs 78532068566406316675611635720434193405248238573309455700708638639692780958210 4066
UVM_INFO @ 202745555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 34897626568512373970331598146979674968133279047185942700333613711680240791067 2341
UVM_INFO @ 291808902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_stress_all 77905726431317120537217464176700638466695278227649723375915095839499557411926 9843
UVM_INFO @ 820715465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---