Simulation Results: rom_ctrl/32kb

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.83 %
  • code
  • 79.59 %
  • assert
  • 96.80 %
  • func
  • 84.09 %
  • block
  • 78.48 %
  • line
  • 78.74 %
  • branch
  • 79.30 %
  • toggle
  • 84.14 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
77.78%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 1365.750us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 2.000s 84.838us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 56.157us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 62.298us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 274.614us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 57.531us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 56.157us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 274.614us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 56.716us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.000s 64.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 168.879us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 4.000s 279.746us 1 1 100.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 51.503us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 507.922us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 507.922us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 2.000s 84.838us 1 1 100.00
rom_ctrl_csr_rw 2.000s 56.157us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 274.614us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 104.170us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 2.000s 84.838us 1 1 100.00
rom_ctrl_csr_rw 2.000s 56.157us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 274.614us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 104.170us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 113.124us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 122.000s 2528.458us 1 1 100.00
rom_ctrl_tl_intg_err 15.000s 1608.471us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 122.000s 2528.458us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 122.000s 2528.458us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 122.000s 2528.458us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 122.000s 2528.458us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 1365.750us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 1365.750us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 1365.750us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 15.000s 1608.471us 1 1 100.00
sec_cm_bus_local_esc 0 2 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 113.124us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 122.000s 2528.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 85077911564170969250559938732818709469154491505159403513191035903415039204580 None
rom_ctrl_kmac_err_chk 53790343191415284882091405005514466298605779662546422029926744441955836206037 None
rom_ctrl_stress_all_with_rand_reset 54735006724161576811967939994303807072979161265079447607029444179268671902444 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 87455594144153181823249203339046328871537583683841525557781748171025710891366 88
UVM_INFO @ 168878995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---