Simulation Results: rom_ctrl/64kb

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.08 %
  • code
  • 79.81 %
  • assert
  • 97.23 %
  • func
  • 96.20 %
  • block
  • 78.57 %
  • line
  • 78.92 %
  • branch
  • 79.53 %
  • toggle
  • 84.61 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 1064.708us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 82.793us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 54.532us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 201.700us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 60.143us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 54.893us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 54.532us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 60.143us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 57.473us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 57.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 5.000s 327.661us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 18.000s 1441.597us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.000s 736.039us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 73.935us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 559.243us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 559.243us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 82.793us 1 1 100.00
rom_ctrl_csr_rw 3.000s 54.532us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 60.143us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 63.205us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 82.793us 1 1 100.00
rom_ctrl_csr_rw 3.000s 54.532us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 60.143us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 63.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 21.000s 4128.631us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 150.000s 391.993us 1 1 100.00
rom_ctrl_tl_intg_err 27.000s 123.975us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 150.000s 391.993us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 150.000s 391.993us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 150.000s 391.993us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 150.000s 391.993us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 1064.708us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 1064.708us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 1064.708us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 27.000s 123.975us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 6.000s 736.039us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 21.000s 4128.631us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 150.000s 391.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 18.000s 1718.408us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 85955988415035684287705528389022823509336690955692123961076545144897120881764 88
UVM_INFO @ 327661391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_corrupt_sig_fatal_chk 61852827682008722729282190688217085389239614537694442774189898319602189093670 None