Simulation Results: rstmgr

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.08 %
  • code
  • 99.19 %
  • assert
  • 98.35 %
  • func
  • 96.69 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.52 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.860s 76.137us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.520s 93.128us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.210s 35.601us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.500s 82.432us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.280s 35.371us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.020s 96.477us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.210s 35.601us 1 1 100.00
rstmgr_csr_aliasing 1.280s 35.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 2.590s 224.035us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.400s 44.016us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.600s 73.349us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 7.410s 690.733us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 7.410s 690.733us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 7.410s 690.733us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 7.410s 690.733us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 16.300s 2180.938us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.300s 38.351us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.860s 68.908us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.860s 68.908us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.520s 93.128us 1 1 100.00
rstmgr_csr_rw 1.210s 35.601us 1 1 100.00
rstmgr_csr_aliasing 1.280s 35.371us 1 1 100.00
rstmgr_same_csr_outstanding 1.370s 41.495us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.520s 93.128us 1 1 100.00
rstmgr_csr_rw 1.210s 35.601us 1 1 100.00
rstmgr_csr_aliasing 1.280s 35.371us 1 1 100.00
rstmgr_same_csr_outstanding 1.370s 41.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 49.380s 6735.410us 1 1 100.00
rstmgr_tl_intg_err 6.350s 639.719us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 49.380s 6735.410us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 49.380s 6735.410us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 6.350s 639.719us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.670s 63.929us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.230s 422.645us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.360s 292.870us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 49.380s 6735.410us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.210s 35.601us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.210s 35.601us 1 1 100.00