Simulation Results

Simulation Results: rv_dm/use_dmi_interface

25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
90.33 %

code
81.12 %

assert
96.74 %

func
93.13 %

block
92.29 %

line
93.00 %

branch
79.05 %

toggle
72.08 %

FSM
80.36 %

Validation stages

V1		92.59%
V2		73.91%
V2S		100.00%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	46.000s	4004.714us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	50.000s	494.657us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	46.000s	185.252us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	56.000s	18368.721us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	44.000s	102.774us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	69.000s	8239.365us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	45.000s	6587.619us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	42.000s	7262.795us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	54.000s	9591.574us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	46.000s	1406.869us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	37.000s	222.375us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	39.000s	831.125us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	43.000s	455.904us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	50.000s	150.107us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	47.000s	975.926us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	45.000s	171.820us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	39.000s	1101.895us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	46.000s	1406.869us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	37.000s	170.002us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	40.000s	276.806us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	39.000s	831.125us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	38.000s	28.738us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	49.000s	282.055us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	39.000s	485.161us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	98.000s	7899.062us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	53.000s	4713.029us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	47.000s	59.956us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	53.000s	4713.029us	1	1	100.00
	rv_dm_csr_rw	39.000s	485.161us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	39.000s	78.773us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	38.000s	90.711us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	46.000s	4004.714us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	42.000s	546.239us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	52.000s	470.556us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	39.000s	226.866us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	39.000s	469.023us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	50.000s	1921.626us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	53.000s	201.008us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	47.000s	1289.995us	0	1	0.00
sba_autoincrement				1	1	100.00
	rv_dm_autoincr_sba_tl_access	49.000s	2060.107us	1	1	100.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	39.000s	215.383us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	44.000s	1029.130us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	45.000s	110.704us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	54.000s	63.684us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	50.000s	6574.545us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	79.000s	1897.202us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	48.000s	101.440us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	44.000s	140.328us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	36.000s	118.370us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	48.000s	446.391us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	48.000s	446.391us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	53.000s	4713.029us	1	1	100.00
	rv_dm_csr_hw_reset	49.000s	282.055us	1	1	100.00
	rv_dm_csr_rw	39.000s	485.161us	1	1	100.00
	rv_dm_same_csr_outstanding	54.000s	867.028us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	53.000s	4713.029us	1	1	100.00
	rv_dm_csr_hw_reset	49.000s	282.055us	1	1	100.00
	rv_dm_csr_rw	39.000s	485.161us	1	1	100.00
	rv_dm_same_csr_outstanding	54.000s	867.028us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	48.000s	2858.843us	1	1	100.00
	rv_dm_tl_intg_err	60.000s	6003.429us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	60.000s	6003.429us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	44.000s	1029.130us	1	1	100.00
	rv_dm_debug_disabled	42.000s	127.065us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	44.000s	1029.130us	1	1	100.00
	rv_dm_debug_disabled	42.000s	127.065us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	46.000s	4004.714us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	45.000s	226.889us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	37.000s	212.071us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	37.000s	212.071us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	45.000s	226.889us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	44.000s	772.181us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	381.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				3 test runs
	rv_dm_hart_unavail	18638034555836577061470631005097104756464525496317237497471297802704077837559	87	UVM_INFO @ 63683974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	3162298531275075502853457239610822264037096788754928273205989744782834792550	88	UVM_INFO @ 140327881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	35321805992395287359627465192189443144220125044121129432859600107362047361417	109	UVM_INFO @ 772180646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	50553942216336799614265939288177719151284358038442517462232047883421361305210	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10275
	rv_dm_bad_sba_tl_access	94194346191673103591878865356594928429197061564701707867820301863987421242002	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23817
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	1356325675328755030205881788845173647944069380395474851543221581443605818063	107	UVM_INFO @ 201007572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	70932019143777520165542419605225320629010892158825372048047930714717874773860	87	UVM_INFO @ 455903619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	113025358067206788601242492768638078394451121993457038201330987901349431417251	87	UVM_INFO @ 215383491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23868) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	42675072746906944874794214582128588897603720439398824123425903372809877980436	87	). UVM_INFO @ 28737800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	111019213941668807797313404889691981908153163537766740635990242328778812420582	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---