Simulation Results: rv_timer

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 96.16 %
  • code
  • 90.39 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 72.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 24.575us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 48.060us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 17.736us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 304.622us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.686us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 18.277us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 17.736us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.686us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 144.475us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 3.000s 1050.262us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 539.000s 1481565.331us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 539.000s 1481565.331us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 10.000s 222.570us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 109.674us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 13.993us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 148.318us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 148.318us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 48.060us 1 1 100.00
rv_timer_csr_rw 1.000s 17.736us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.686us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 152.329us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 48.060us 1 1 100.00
rv_timer_csr_rw 1.000s 17.736us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.686us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 152.329us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 333.854us 1 1 100.00
rv_timer_tl_intg_err 1.000s 131.950us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 131.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 110.203us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 234.500us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 44.000s 21570.853us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 103091173605894676296173782704969095386520801007608653356724767795919667999590 84
UVM_INFO @ 110202686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 87353432130990643262418251411397759361651520670662759404946906791404129569070 84
UVM_INFO @ 234499657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---