Simulation Results: spi_device/1r1w

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.18 %
  • code
  • 89.53 %
  • assert
  • 95.40 %
  • func
  • 67.61 %
  • block
  • 98.35 %
  • line
  • 98.77 %
  • branch
  • 97.02 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 247.000s 101863.128us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 123.367us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 4.000s 72.704us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 13.000s 1461.645us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 3.000s 174.226us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 452.522us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 4.000s 72.704us 1 1 100.00
spi_device_csr_aliasing 3.000s 174.226us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 38.205us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 127.411us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 41.824us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 2.986us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 5.695us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 77.815us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 77.815us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 12.000s 1248.731us 1 1 100.00
spi_device_tpm_sts_read 2.000s 93.828us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 37.000s 1250.483us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 59.000s 26834.833us 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 26.000s 10190.578us 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 26.000s 10190.578us 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 13.000s 697.253us 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 13.000s 697.253us 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 13.000s 697.253us 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 13.000s 697.253us 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 13.000s 697.253us 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.000s 179.283us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 12.000s 312.259us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 12.000s 312.259us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 12.000s 312.259us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 9.000s 212.428us 1 1 100.00
spi_device_read_buffer_direct 10.000s 1279.904us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 12.000s 312.259us 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 283.000s 244366.754us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 8.000s 404.803us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 8.000s 404.803us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 78.000s 12255.203us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 247.000s 101863.128us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 790.000s 70863.883us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 31.000s 4444.235us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 12.564us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 108.274us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.000s 361.650us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.000s 361.650us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 123.367us 1 1 100.00
spi_device_csr_rw 4.000s 72.704us 1 1 100.00
spi_device_csr_aliasing 3.000s 174.226us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 272.631us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 123.367us 1 1 100.00
spi_device_csr_rw 4.000s 72.704us 1 1 100.00
spi_device_csr_aliasing 3.000s 174.226us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 272.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 246.679us 1 1 100.00
spi_device_tl_intg_err 19.000s 736.727us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 19.000s 736.727us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 93076529044586197331455454895353443071697167688834410396996754254979323784290 87
UVM_ERROR @ 2411678 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[975] not found within the scope .
UVM_ERROR @ 2411678 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[975] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 75776284676405591788954318185873177715672650074336790477699957857651043416011 85
UVM_ERROR @ 3294143 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x119 [100011001] vs 0x0 [0])
UVM_ERROR @ 3375143 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x164 [101100100] vs 0x0 [0])
UVM_ERROR @ 3396143 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x17b [101111011] vs 0x0 [0])
UVM_ERROR @ 3486143 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x23f [1000111111] vs 0x0 [0])