Simulation Results: spi_host

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.74 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 88.66 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 17.000s 3385.957us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 17.865us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 15.260us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 82.057us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 32.419us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 25.906us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 15.260us 1 1 100.00
spi_host_csr_aliasing 1.000s 32.419us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 14.867us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 42.034us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 44.677us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 115.800us 1 1 100.00
spi_host_error_cmd 2.000s 16.193us 1 1 100.00
spi_host_event 16.000s 1029.633us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 4.000s 440.706us 1 1 100.00
speed 1 1 100.00
spi_host_speed 4.000s 440.706us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 4.000s 440.706us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 170.000s 8261.996us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 152.090us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 108.364us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 4.000s 440.706us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 4.000s 440.706us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 17.000s 3385.957us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 17.000s 3385.957us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 16.000s 873.451us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 238.623us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 32.000s 2769.639us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 201.657us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 115.800us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 40.028us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 22.009us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 28.788us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 28.788us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 17.865us 1 1 100.00
spi_host_csr_rw 2.000s 15.260us 1 1 100.00
spi_host_csr_aliasing 1.000s 32.419us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 30.494us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 17.865us 1 1 100.00
spi_host_csr_rw 2.000s 15.260us 1 1 100.00
spi_host_csr_aliasing 1.000s 32.419us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 30.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 292.198us 1 1 100.00
spi_host_sec_cm 1.000s 159.701us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 292.198us 1 1 100.00