Simulation Results: sram_ctrl/main

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.19 %
  • code
  • 94.28 %
  • assert
  • 97.69 %
  • func
  • 93.60 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 90.91 %
  • toggle
  • 91.70 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.000s 6209.794us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 14.084us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.459us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 57.166us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 45.392us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1236.960us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 14.459us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 45.392us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 165.000s 17634.716us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 117.000s 6635.171us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 28.000s 5021.764us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 249.000s 36990.827us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 160.000s 13344.918us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 79.000s 11639.567us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 77.000s 72430.514us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 41.000s 5483.973us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.000s 2812.490us 1 1 100.00
sram_ctrl_partial_access_b2b 370.000s 42927.935us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 1805.432us 1 1 100.00
sram_ctrl_throughput_w_partial_write 6.000s 1429.044us 1 1 100.00
sram_ctrl_throughput_w_readback 6.000s 679.165us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 499.351us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1297.640us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 30.000s 8108.706us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.935us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 94.047us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 94.047us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.084us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.459us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 45.392us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 17.340us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.084us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.459us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 45.392us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 17.340us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.000s 7248.250us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 1746.141us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 376.189us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 1746.141us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 376.189us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 499.351us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 499.351us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.459us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 41.000s 5483.973us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 41.000s 5483.973us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 41.000s 5483.973us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 77.000s 72430.514us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.000s 7248.250us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 6209.794us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 6209.794us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 41.000s 5483.973us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 1746.141us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 77.000s 72430.514us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 1746.141us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1746.141us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.000s 6209.794us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1746.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 24.000s 2800.048us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 101720453390663374054063023907605842880062832285633341495470131047278116636489 None
sram_ctrl_mubi_enc_err 115360292149181375614964194250587525963211732386691942078233053759042124306292 None