Simulation Results: sram_ctrl/ret

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.25 %
  • code
  • 81.46 %
  • assert
  • 98.08 %
  • func
  • 94.20 %
  • block
  • 91.78 %
  • line
  • 93.41 %
  • branch
  • 87.44 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 262.706us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 26.004us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 40.043us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 434.016us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.354us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 241.617us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 40.043us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.354us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 12.000s 3387.753us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 375.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 388.167us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 128.000s 7985.379us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 9.000s 572.314us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 17.000s 1049.368us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 849.416us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 1251.433us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 143.161us 1 1 100.00
sram_ctrl_partial_access_b2b 299.000s 17115.495us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 258.621us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 78.016us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 69.939us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 2.000s 484.120us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 29.081us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 23.000s 1262.024us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 77.053us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 79.899us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 79.899us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 26.004us 1 1 100.00
sram_ctrl_csr_rw 1.000s 40.043us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.354us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 13.781us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 26.004us 1 1 100.00
sram_ctrl_csr_rw 1.000s 40.043us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.354us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 13.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 580.533us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1266.513us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 450.334us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1266.513us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 450.334us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 2.000s 484.120us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 2.000s 484.120us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 40.043us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 1251.433us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 1251.433us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 1251.433us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 849.416us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 580.533us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 262.706us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 262.706us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 1251.433us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1266.513us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 849.416us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1266.513us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1266.513us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 262.706us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1266.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 36.000s 789.110us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 34681642203418793358988034835839675100561716129384124870693784907986546391490 None
sram_ctrl_mubi_enc_err 114555274958457366736227723039787477526932593067209312107605256554747797359242 None