Simulation Results: uart

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 93.83 %
  • code
  • 92.53 %
  • assert
  • 98.27 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 763.317us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 16.366us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 90.493us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 576.979us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 15.090us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 19.789us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 90.493us 1 1 100.00
uart_csr_aliasing 2.000s 15.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 117.000s 252198.454us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 763.317us 1 1 100.00
uart_tx_rx 117.000s 252198.454us 1 1 100.00
parity_error 2 2 100.00
uart_intr 44.000s 49429.200us 1 1 100.00
uart_rx_parity_err 41.000s 79209.278us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 117.000s 252198.454us 1 1 100.00
uart_intr 44.000s 49429.200us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 35.000s 64735.802us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 24.000s 226809.759us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 41.000s 158080.364us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 44.000s 49429.200us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 44.000s 49429.200us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 44.000s 49429.200us 1 1 100.00
perf 1 1 100.00
uart_perf 134.000s 18673.960us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 8.000s 5719.566us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 8.000s 5719.566us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 4.000s 7086.385us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.000s 410.320us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 22.000s 6230.837us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 27.000s 4078.342us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 164.000s 93781.306us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 696.000s 232712.022us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 14.379us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 25.629us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 3.000s 411.938us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 3.000s 411.938us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 16.366us 1 1 100.00
uart_csr_rw 1.000s 90.493us 1 1 100.00
uart_csr_aliasing 2.000s 15.090us 1 1 100.00
uart_same_csr_outstanding 1.000s 144.670us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 16.366us 1 1 100.00
uart_csr_rw 1.000s 90.493us 1 1 100.00
uart_csr_aliasing 2.000s 15.090us 1 1 100.00
uart_same_csr_outstanding 1.000s 144.670us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 123.895us 1 1 100.00
uart_tl_intg_err 2.000s 360.374us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 360.374us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 26.000s 2348.392us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:376) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 5874834179697203630742942829469075173524938277909503814044613970222081722707 84
UVM_ERROR @ 2252820788 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 6, clk_pulses: 0
UVM_ERROR @ 2253070787 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (70 [0x46] vs 119 [0x77]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2253237453 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2253320786 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (70 [0x46] vs 223 [0xdf]) reg name: uart_reg_block.rdata