Simulation Results: ac_range_check

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.00 %
  • code
  • 93.18 %
  • assert
  • 97.75 %
  • func
  • 58.07 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.36 %
Validation stages
V1
85.71%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 0 1 0.00
ac_range_check_smoke 43.000s 7210.490us 0 1 0.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 50.000s 2175.111us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 10.000s 86.052us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 9.000s 94.277us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 47.000s 10573.008us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 11.000s 105.257us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 9.000s 54.785us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 9.000s 94.277us 1 1 100.00
ac_range_check_csr_aliasing 11.000s 105.257us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 11.000s 260.642us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 32.000s 1514.750us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 362.000s 11871.629us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 9.000s 27.264us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 9.000s 78.984us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 4.000s 75.996us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 4.000s 75.996us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 86.052us 1 1 100.00
ac_range_check_csr_rw 9.000s 94.277us 1 1 100.00
ac_range_check_csr_aliasing 11.000s 105.257us 1 1 100.00
ac_range_check_same_csr_outstanding 8.000s 837.836us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 86.052us 1 1 100.00
ac_range_check_csr_rw 9.000s 94.277us 1 1 100.00
ac_range_check_csr_aliasing 11.000s 105.257us 1 1 100.00
ac_range_check_same_csr_outstanding 8.000s 837.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 387.733us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 387.733us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 387.733us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 15.000s 387.733us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 70.000s 5247.106us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 5.000s 37.004us 1 1 100.00
ac_range_check_tl_intg_err 10.000s 709.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 380.000s 49600.440us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 37.000s 5865.533us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:373) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 1 test run
ac_range_check_smoke 66247278191821046148503786702954865134874485541274777109997173383792346570866 4174
UVM_INFO @ 7210489839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---