Simulation Results: aes/gcm_unmasked

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 85.13 %
  • code
  • 90.82 %
  • assert
  • 97.75 %
  • func
  • 66.82 %
  • block
  • 90.19 %
  • line
  • 92.21 %
  • branch
  • 82.31 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 65.819us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 63.994us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 75.025us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 66.275us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 258.746us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 77.282us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 90.582us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 66.275us 1 1 100.00
aes_csr_aliasing 2.000s 77.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 63.994us 1 1 100.00
aes_config_error 6.000s 496.969us 1 1 100.00
aes_stress 3.000s 66.694us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 63.994us 1 1 100.00
aes_config_error 6.000s 496.969us 1 1 100.00
aes_stress 3.000s 66.694us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 66.694us 1 1 100.00
aes_b2b 7.000s 477.360us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 66.694us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 63.994us 1 1 100.00
aes_config_error 6.000s 496.969us 1 1 100.00
aes_stress 3.000s 66.694us 1 1 100.00
aes_alert_reset 2.000s 98.595us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 90.953us 1 1 100.00
aes_config_error 6.000s 496.969us 1 1 100.00
aes_alert_reset 2.000s 98.595us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 219.532us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 306.279us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 98.595us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 66.694us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 66.694us 1 1 100.00
aes_sideload 3.000s 124.990us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 77.644us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 15.000s 1011.841us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 74.004us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 165.560us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 165.560us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 75.025us 1 1 100.00
aes_csr_rw 2.000s 66.275us 1 1 100.00
aes_csr_aliasing 2.000s 77.282us 1 1 100.00
aes_same_csr_outstanding 2.000s 132.791us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 75.025us 1 1 100.00
aes_csr_rw 2.000s 66.275us 1 1 100.00
aes_csr_aliasing 2.000s 77.282us 1 1 100.00
aes_same_csr_outstanding 2.000s 132.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 1.000s 17.866us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 67.776us 0 1 0.00
aes_control_fi 2.000s 66.114us 1 1 100.00
aes_cipher_fi 2.000s 45.864us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 155.026us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 155.026us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 155.026us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 155.026us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 6.000s 1446.589us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 919.228us 1 1 100.00
aes_tl_intg_err 3.000s 441.870us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 441.870us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 98.595us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 155.026us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 155.026us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 63.994us 1 1 100.00
aes_stress 3.000s 66.694us 1 1 100.00
aes_alert_reset 2.000s 98.595us 1 1 100.00
aes_core_fi 3.000s 397.057us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 6.000s 496.969us 1 1 100.00
aes_stress 3.000s 66.694us 1 1 100.00
aes_core_fi 3.000s 397.057us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 155.026us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 57.427us 1 1 100.00
aes_stress 3.000s 66.694us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 66.694us 1 1 100.00
aes_sideload 3.000s 124.990us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 57.427us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 57.427us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 57.427us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 57.427us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 57.427us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 66.694us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 66.694us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 67.776us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 67.776us 0 1 0.00
aes_control_fi 2.000s 66.114us 1 1 100.00
aes_cipher_fi 2.000s 45.864us 1 1 100.00
aes_ctr_fi 2.000s 102.563us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 67.776us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 67.776us 0 1 0.00
aes_control_fi 2.000s 66.114us 1 1 100.00
aes_cipher_fi 2.000s 45.864us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 45.864us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 67.776us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 67.776us 0 1 0.00
aes_control_fi 2.000s 66.114us 1 1 100.00
aes_ctr_fi 2.000s 102.563us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 67.776us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 67.776us 0 1 0.00
aes_control_fi 2.000s 66.114us 1 1 100.00
aes_cipher_fi 2.000s 45.864us 1 1 100.00
aes_ctr_fi 2.000s 102.563us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 98.595us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 67.776us 0 1 0.00
aes_control_fi 2.000s 66.114us 1 1 100.00
aes_cipher_fi 2.000s 45.864us 1 1 100.00
aes_ctr_fi 2.000s 102.563us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 67.776us 0 1 0.00
aes_control_fi 2.000s 66.114us 1 1 100.00
aes_cipher_fi 2.000s 45.864us 1 1 100.00
aes_ctr_fi 2.000s 102.563us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 67.776us 0 1 0.00
aes_control_fi 2.000s 66.114us 1 1 100.00
aes_ctr_fi 2.000s 102.563us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 67.776us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 67.776us 0 1 0.00
aes_control_fi 2.000s 66.114us 1 1 100.00
aes_cipher_fi 2.000s 45.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 6.000s 652.657us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 45204208058240275385769500512596890537084896928727779891133202953549991190049 584
UVM_INFO @ 17865624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 78771621462194609312687028231300817462618888328572991141465138313739715319974 4847
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:104) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 41667637030905347283875828655800125230886433563597968577598104119784725097982 248
UVM_INFO @ 652656935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---