Simulation Results: alert_handler

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.19 %
  • code
  • 89.09 %
  • assert
  • 97.84 %
  • func
  • 74.64 %
  • line
  • 99.65 %
  • branch
  • 98.24 %
  • cond
  • 91.36 %
  • toggle
  • 86.87 %
  • FSM
  • 69.35 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 41.890s 492.859us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 10.880s 286.377us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.710s 587.226us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 665.340s 10619.580us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 57.510s 1022.952us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.890s 304.218us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.710s 587.226us 1 1 100.00
alert_handler_csr_aliasing 57.510s 1022.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 384.430s 23344.588us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 71.020s 4761.305us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2035.030s 50266.411us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 8.550s 468.552us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 41.890s 492.859us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 11.990s 641.887us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 30.120s 4012.822us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 110.380s 5566.706us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2931.770s 57500.561us 1 1 100.00
alert_handler_lpg_stub_clk 3263.280s 256013.063us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2903.550s 55041.429us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 9.940s 120.468us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 4.150s 93.445us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.500s 31.285us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 10.960s 190.226us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 10.960s 190.226us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 10.880s 286.377us 1 1 100.00
alert_handler_csr_rw 5.710s 587.226us 1 1 100.00
alert_handler_csr_aliasing 57.510s 1022.952us 1 1 100.00
alert_handler_same_csr_outstanding 10.060s 743.512us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 10.880s 286.377us 1 1 100.00
alert_handler_csr_rw 5.710s 587.226us 1 1 100.00
alert_handler_csr_aliasing 57.510s 1022.952us 1 1 100.00
alert_handler_same_csr_outstanding 10.060s 743.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 246.340s 12404.573us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 246.340s 12404.573us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 246.340s 12404.573us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 246.340s 12404.573us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 679.420s 19511.795us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 17.740s 1568.529us 1 1 100.00
alert_handler_tl_intg_err 98.420s 4961.226us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 98.420s 4961.226us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 246.340s 12404.573us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 41.890s 492.859us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 41.890s 492.859us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 41.890s 492.859us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 41.890s 492.859us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.550s 468.552us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2931.770s 57500.561us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.550s 468.552us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2035.030s 50266.411us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2035.030s 50266.411us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.740s 1568.529us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.740s 1568.529us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.740s 1568.529us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.740s 1568.529us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 17.740s 1568.529us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.740s 1568.529us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.740s 1568.529us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.740s 1568.529us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 17.740s 1568.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 26.870s 1987.181us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 4559249453734448637969171613566468674198763937943079134921295466365428370668 106
UVM_INFO @ 5566705805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 85188616545121971609591953209539143251218299466346120542625801083426934323167 192
UVM_INFO @ 120467562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 111831737330210215123040606388919579405719473594460748963250901630769277685798 99
UVM_INFO @ 1987181457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---