Simulation Results: clkmgr

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.67 %
  • code
  • 69.40 %
  • assert
  • 90.08 %
  • func
  • 61.52 %
  • line
  • 82.27 %
  • branch
  • 87.53 %
  • cond
  • 78.33 %
  • toggle
  • 98.87 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.790s 58.191us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.160s 23.305us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.910s 3.947us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 6.400s 656.939us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.070s 148.735us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.330s 27.799us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.910s 3.947us 0 1 0.00
clkmgr_csr_aliasing 2.070s 148.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.550s 42.519us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 2.720s 117.729us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.040s 35.085us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.790s 58.191us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.990s 5.526us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.960s 4.781us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.990s 5.526us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 2.230s 94.594us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.110s 17.565us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 5.810s 288.997us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 5.810s 288.997us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.160s 23.305us 1 1 100.00
clkmgr_csr_rw 0.910s 3.947us 0 1 0.00
clkmgr_csr_aliasing 2.070s 148.735us 1 1 100.00
clkmgr_same_csr_outstanding 0.840s 7.006us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.160s 23.305us 1 1 100.00
clkmgr_csr_rw 0.910s 3.947us 0 1 0.00
clkmgr_csr_aliasing 2.070s 148.735us 1 1 100.00
clkmgr_same_csr_outstanding 0.840s 7.006us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 9.760s 749.778us 1 1 100.00
clkmgr_tl_intg_err 1.170s 17.425us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.910s 64.061us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.910s 64.061us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.910s 64.061us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.910s 64.061us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.920s 3.873us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.170s 17.425us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.990s 5.526us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.960s 4.781us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.910s 64.061us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.130s 81.753us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.910s 3.947us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 9.760s 749.778us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.910s 3.947us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.910s 3.947us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 9.760s 749.778us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.950s 3.276us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 27.100s 1498.698us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency 78327797778311658728106060823798974910238944699888493161618659750045435272551 81
UVM_INFO @ 5525630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 84058000031886381660674255375467961016132885255714192929026280991665446395051 196
UVM_INFO @ 1498697851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 69051909814362483279194880066442438633032299602765107183982810553896063012410 81
UVM_INFO @ 94593601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 44093210463812784894654212006648800089380917332086595460766939695912593820041 81
UVM_INFO @ 3873500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 2087874369423815196130773856070912170828760637220430562301188166550681196789 91
UVM_INFO @ 17425235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 65685626958165971075034963445510875692233401071371751851083190867263303619573 81
UVM_INFO @ 3946587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 70648265471359974674861459159221914546527512755277690542392917587090436732957 84
UVM_INFO @ 4781148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 111885821320137723262450064822893852628162023974111862741784267788208924365502 80
UVM_INFO @ 3275607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 41023588970782911663589374597678341798357458330344203918910956731573673890015 81
UVM_INFO @ 656938510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 76331166517973855297115907083977208013126153357134324148860876591461407788845 81
UVM_INFO @ 7006497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_csr_mem_rw_with_rand_reset 24357073846344206129651702420561317956374842263859882404416355223802446639570 82
UVM_INFO @ 27798877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---