Simulation Results: csrng

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.95 %
  • code
  • 92.25 %
  • assert
  • 94.54 %
  • func
  • 80.07 %
  • block
  • 96.89 %
  • line
  • 97.66 %
  • branch
  • 92.26 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 4.000s 44.273us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 4.000s 54.683us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 59.250us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 20.000s 1114.521us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 25.154us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 4.000s 87.838us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 59.250us 1 1 100.00
csrng_csr_aliasing 3.000s 25.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
alerts 1 1 100.00
csrng_alert 5.000s 187.547us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 25.000s 1656.839us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 25.000s 1656.839us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 614.000s 33522.332us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 4.000s 41.087us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 63.229us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 10.000s 276.189us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 10.000s 276.189us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 4.000s 54.683us 1 1 100.00
csrng_csr_rw 3.000s 59.250us 1 1 100.00
csrng_csr_aliasing 3.000s 25.154us 1 1 100.00
csrng_same_csr_outstanding 4.000s 73.077us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 4.000s 54.683us 1 1 100.00
csrng_csr_rw 3.000s 59.250us 1 1 100.00
csrng_csr_aliasing 3.000s 25.154us 1 1 100.00
csrng_same_csr_outstanding 4.000s 73.077us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 215.028us 1 1 100.00
csrng_tl_intg_err 6.000s 127.689us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 3.000s 20.110us 1 1 100.00
csrng_csr_rw 3.000s 59.250us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 5.000s 187.547us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 614.000s 33522.332us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
csrng_sec_cm 5.000s 215.028us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
csrng_sec_cm 5.000s 215.028us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
csrng_sec_cm 5.000s 215.028us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
csrng_sec_cm 5.000s 215.028us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
csrng_sec_cm 5.000s 215.028us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 5.000s 187.547us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 614.000s 33522.332us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 5.000s 187.547us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 6.000s 127.689us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
csrng_sec_cm 5.000s 215.028us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
csrng_sec_cm 5.000s 215.028us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 104.338us 1 1 100.00
csrng_err 3.000s 24.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 40.000s 2243.937us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 1 test run
csrng_stress_all_with_rand_reset 41386882256606400615693162305411705265483785903116275585175587822928753983330 143
UVM_INFO @ 2243937320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---