Simulation Results: dma

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 81.35 %
  • code
  • 90.76 %
  • assert
  • 96.61 %
  • func
  • 56.69 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 8.000s 460.927us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 7.000s 952.764us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 285.868us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 32.911us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 20.426us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 8.000s 573.180us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 43.542us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 22.115us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 20.426us 1 1 100.00
dma_csr_aliasing 2.000s 43.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 92.000s 15781.580us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 317.000s 22940.738us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 152.000s 21335.236us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 152.000s 21335.236us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 317.000s 22940.738us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 125.000s 9354.772us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 152.000s 21335.236us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 13.000s 862.530us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 180.000s 25877.575us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 15.667us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 3.000s 12.785us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 165.671us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 165.671us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 32.911us 1 1 100.00
dma_csr_rw 2.000s 20.426us 1 1 100.00
dma_csr_aliasing 2.000s 43.542us 1 1 100.00
dma_same_csr_outstanding 4.000s 138.119us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 32.911us 1 1 100.00
dma_csr_rw 2.000s 20.426us 1 1 100.00
dma_csr_aliasing 2.000s 43.542us 1 1 100.00
dma_same_csr_outstanding 4.000s 138.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 17.000s 1460.924us 1 1 100.00
dma_generic_stress 125.000s 9354.772us 1 1 100.00
dma_handshake_stress 152.000s 21335.236us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 10.000s 297.113us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 5.000s 362.567us 1 1 100.00
dma_sec_cm 2.000s 16.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 87.000s 14915.991us 1 1 100.00
dma_longer_transfer 11.000s 601.212us 1 1 100.00
dma_stress_all_with_rand_reset 18.000s 979.288us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 110916164768683631132017784210189615510544649674510239764681440624857697326065 113
UVM_INFO @ 979287682ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---