Simulation Results: edn/edn0

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 73.64 %
  • code
  • 79.79 %
  • assert
  • 93.58 %
  • func
  • 47.55 %
  • block
  • 92.99 %
  • line
  • 96.25 %
  • branch
  • 85.01 %
  • toggle
  • 65.02 %
  • FSM
  • 72.87 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 3.000s 18.028us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 3.000s 15.395us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 24.098us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 383.889us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 25.987us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 51.685us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 24.098us 1 1 100.00
edn_csr_aliasing 2.000s 25.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 4.000s 359.163us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 4.000s 359.163us 1 1 100.00
genbits 1 1 100.00
edn_genbits 4.000s 359.163us 1 1 100.00
interrupts 1 1 100.00
edn_intr 3.000s 39.054us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 24.589us 1 1 100.00
errs 1 1 100.00
edn_err 3.000s 41.959us 1 1 100.00
disable 2 2 100.00
edn_disable 3.000s 25.089us 1 1 100.00
edn_disable_auto_req_mode 3.000s 116.943us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 10.000s 55.116us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 3.000s 43.328us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 3.000s 48.390us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 5.000s 341.472us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 5.000s 341.472us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 3.000s 15.395us 1 1 100.00
edn_csr_rw 2.000s 24.098us 1 1 100.00
edn_csr_aliasing 2.000s 25.987us 1 1 100.00
edn_same_csr_outstanding 3.000s 67.286us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 3.000s 15.395us 1 1 100.00
edn_csr_rw 2.000s 24.098us 1 1 100.00
edn_csr_aliasing 2.000s 25.987us 1 1 100.00
edn_same_csr_outstanding 3.000s 67.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 9.000s 416.337us 1 1 100.00
edn_tl_intg_err 3.000s 360.674us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 15.769us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 24.589us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 9.000s 416.337us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 9.000s 416.337us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 9.000s 416.337us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 9.000s 416.337us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 24.589us 1 1 100.00
edn_sec_cm 9.000s 416.337us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 24.589us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 360.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 63.000s 3163.963us 1 1 100.00