Simulation Results: edn/edn1

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.71 %
  • code
  • 83.55 %
  • assert
  • 98.44 %
  • func
  • 78.15 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 87.15 %
  • toggle
  • 93.45 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.130s 23.123us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.140s 51.532us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.070s 40.502us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.700s 303.735us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.180s 19.853us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.740s 23.604us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.070s 40.502us 1 1 100.00
edn_csr_aliasing 1.180s 19.853us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.350s 52.281us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.350s 52.281us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.350s 52.281us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.170s 35.180us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.500s 32.419us 1 1 100.00
errs 1 1 100.00
edn_err 1.170s 20.678us 1 1 100.00
disable 2 2 100.00
edn_disable 1.120s 14.096us 1 1 100.00
edn_disable_auto_req_mode 1.100s 59.613us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.610s 260.461us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.060s 13.226us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.160s 50.457us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.340s 44.642us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.340s 44.642us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.140s 51.532us 1 1 100.00
edn_csr_rw 1.070s 40.502us 1 1 100.00
edn_csr_aliasing 1.180s 19.853us 1 1 100.00
edn_same_csr_outstanding 1.440s 52.100us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.140s 51.532us 1 1 100.00
edn_csr_rw 1.070s 40.502us 1 1 100.00
edn_csr_aliasing 1.180s 19.853us 1 1 100.00
edn_same_csr_outstanding 1.440s 52.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.300s 678.888us 1 1 100.00
edn_tl_intg_err 2.190s 81.689us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.140s 83.626us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.500s 32.419us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.300s 678.888us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.300s 678.888us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.300s 678.888us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.300s 678.888us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.500s 32.419us 1 1 100.00
edn_sec_cm 4.300s 678.888us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.500s 32.419us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.190s 81.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 174.470s 12752.848us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 92541421319037443878165780459544985052355022220631721240864792113928197029031 289
UVM_INFO @ 12752848287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---