Simulation Results: hmac

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.36 %
  • code
  • 83.15 %
  • assert
  • 95.87 %
  • func
  • 29.06 %
  • block
  • 97.42 %
  • line
  • 98.35 %
  • branch
  • 93.52 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 19.000s 1466.209us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 31.794us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 18.576us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 20.000s 1979.007us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 664.402us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 36.841us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 18.576us 1 1 100.00
hmac_csr_aliasing 3.000s 664.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 141.000s 11280.592us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 73.000s 4871.807us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 334.000s 83170.731us 1 1 100.00
hmac_test_sha384_vectors 526.000s 16885.666us 1 1 100.00
hmac_test_sha512_vectors 32.000s 1570.318us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 264.282us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 1331.522us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 312.490us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 23.000s 21252.760us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 96.000s 8452.746us 1 1 100.00
error 1 1 100.00
hmac_error 146.000s 12006.150us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 152.000s 47423.095us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 19.000s 1466.209us 1 1 100.00
hmac_long_msg 141.000s 11280.592us 1 1 100.00
hmac_back_pressure 73.000s 4871.807us 1 1 100.00
hmac_datapath_stress 96.000s 8452.746us 1 1 100.00
hmac_burst_wr 23.000s 21252.760us 1 1 100.00
hmac_stress_all 455.000s 35854.882us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 19.000s 1466.209us 1 1 100.00
hmac_long_msg 141.000s 11280.592us 1 1 100.00
hmac_back_pressure 73.000s 4871.807us 1 1 100.00
hmac_datapath_stress 96.000s 8452.746us 1 1 100.00
hmac_wipe_secret 152.000s 47423.095us 1 1 100.00
hmac_test_sha256_vectors 334.000s 83170.731us 1 1 100.00
hmac_test_sha384_vectors 526.000s 16885.666us 1 1 100.00
hmac_test_sha512_vectors 32.000s 1570.318us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 264.282us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 1331.522us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 312.490us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 19.000s 1466.209us 1 1 100.00
hmac_long_msg 141.000s 11280.592us 1 1 100.00
hmac_back_pressure 73.000s 4871.807us 1 1 100.00
hmac_datapath_stress 96.000s 8452.746us 1 1 100.00
hmac_burst_wr 23.000s 21252.760us 1 1 100.00
hmac_error 146.000s 12006.150us 1 1 100.00
hmac_wipe_secret 152.000s 47423.095us 1 1 100.00
hmac_test_sha256_vectors 334.000s 83170.731us 1 1 100.00
hmac_test_sha384_vectors 526.000s 16885.666us 1 1 100.00
hmac_test_sha512_vectors 32.000s 1570.318us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 264.282us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 1331.522us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 312.490us 1 1 100.00
hmac_stress_all 455.000s 35854.882us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 455.000s 35854.882us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 39.670us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 20.099us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 192.459us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 192.459us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 31.794us 1 1 100.00
hmac_csr_rw 2.000s 18.576us 1 1 100.00
hmac_csr_aliasing 3.000s 664.402us 1 1 100.00
hmac_same_csr_outstanding 4.000s 213.624us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 31.794us 1 1 100.00
hmac_csr_rw 2.000s 18.576us 1 1 100.00
hmac_csr_aliasing 3.000s 664.402us 1 1 100.00
hmac_same_csr_outstanding 4.000s 213.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 128.532us 1 1 100.00
hmac_tl_intg_err 5.000s 697.374us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 5.000s 697.374us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 19.000s 1466.209us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 143.211us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 97.000s 3968.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 5.000s 532.388us 1 1 100.00