Simulation Results: i2c

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.55 %
  • code
  • 87.17 %
  • assert
  • 97.25 %
  • func
  • 81.22 %
  • block
  • 96.49 %
  • line
  • 95.93 %
  • branch
  • 93.75 %
  • toggle
  • 72.68 %
  • FSM
  • 86.33 %
Validation stages
V1
100.00%
V2
82.93%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 65.000s 10113.828us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 16.000s 2287.409us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 2.000s 28.379us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 2.000s 21.863us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 7.000s 645.229us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 3.000s 26.347us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 3.000s 30.124us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 2.000s 21.863us 1 1 100.00
i2c_csr_aliasing 3.000s 26.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 3.000s 26.560us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 3601.000s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 6.000s 478.116us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 2.000s 96.071us 1 1 100.00
host_fifo_watermark 0 1 0.00
i2c_host_fifo_watermark 3600.000s 0.000us 0 1 0.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 962.000s 1448.569us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 3.000s 113.675us 1 1 100.00
i2c_host_fifo_fmt_empty 38.000s 734.629us 1 1 100.00
i2c_host_fifo_reset_rx 6.000s 139.344us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 296.000s 2466.192us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 15.000s 2456.455us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 5.000s 453.106us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 5.000s 2317.191us 0 1 0.00
target_stress_all 0 1 0.00
i2c_target_stress_all 3600.000s 0.000us 0 1 0.00
target_maxperf 1 1 100.00
i2c_target_perf 9.000s 1667.486us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 19.000s 2645.080us 1 1 100.00
i2c_target_intr_smoke 10.000s 1086.851us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 4.000s 517.570us 1 1 100.00
i2c_target_fifo_reset_tx 3.000s 215.215us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 2166.000s 34104.040us 1 1 100.00
i2c_target_stress_rd 19.000s 2645.080us 1 1 100.00
i2c_target_intr_stress_wr 4.000s 1360.558us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 13.000s 2822.954us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 8.000s 1603.194us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 11.000s 1091.933us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 16.000s 10314.142us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 4.000s 349.435us 1 1 100.00
i2c_target_fifo_watermarks_tx 3.000s 277.476us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 6.000s 478.116us 1 1 100.00
i2c_host_perf_precise 24.000s 2723.256us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 15.000s 2456.455us 1 1 100.00
target_mode_tx_stretch_ctrl 0 1 0.00
i2c_target_tx_stretch_ctrl 2.000s 15.427us 0 1 0.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 5.000s 11957.002us 1 1 100.00
i2c_target_nack_acqfull_addr 5.000s 512.086us 1 1 100.00
i2c_target_nack_txstretch 4.000s 652.450us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 13.000s 437.968us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 4.000s 1602.641us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 3.000s 134.232us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 2.000s 20.330us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 3.000s 170.086us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 3.000s 170.086us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 2.000s 28.379us 1 1 100.00
i2c_csr_rw 2.000s 21.863us 1 1 100.00
i2c_csr_aliasing 3.000s 26.347us 1 1 100.00
i2c_same_csr_outstanding 2.000s 64.584us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 2.000s 28.379us 1 1 100.00
i2c_csr_rw 2.000s 21.863us 1 1 100.00
i2c_csr_aliasing 3.000s 26.347us 1 1 100.00
i2c_same_csr_outstanding 2.000s 64.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 3.000s 250.362us 1 1 100.00
i2c_sec_cm 2.000s 77.647us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 3.000s 250.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 13.000s 2136.290us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 2.000s 154.781us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 6.000s 759.308us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
i2c_host_fifo_watermark 51606133204501300681348663465938746771159791589405671577106491240794396233455 None
i2c_host_stress_all 40477746052793702206832468667794097576388244450609630479730225403948219374123 None
i2c_target_stress_all 60809464116135549018139808997821047456643958025412817782217363971333004079318 None
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 74103842389677695008859766330620860650314661312555825023211002759227201024213 95
UVM_INFO @ 2136289791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 39929963297870760244137238291904763859081622587624012891787920513799212756886 93
UVM_INFO @ 759307893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 1 test run
i2c_host_error_intr 63348487142861921540696772267822910808202523195819972414127752380111328036198 121
UVM_INFO @ 26560292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 32570789414763396108515055539776782739058929272953411248894860956555443528127 93
UVM_INFO @ 2317190575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 77636130426011729443641392993318994738204585660376246199535221584763894402085 87
UVM_INFO @ 154780610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 16341720592115085048807469253354204377829353301928431084005375879478842485068 88
UVM_INFO @ 10314142111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:882) [i2c_target_tx_stretch_ctrl_vseq] Check failed (std::randomize(transfer_lengths) with {transfer_lengths.size() == num_transfers; transfer_lengths.sum() == num_data_total; foreach (transfer_lengths[i]) { transfer_lengths[i] inside {[cfg.min_xfer_len : num_data_total]}; } transfer_lengths[*] > *; transfer_lengths[num_transfers - *] > *;}) Randomization failed! 1 test run
i2c_target_tx_stretch_ctrl 107851791022699752116630542875217515281328226918377867233291059030541330388137 110
UVM_INFO @ 15426722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---