Simulation Results: lc_ctrl/volatile_unlock_disabled

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.59 %
  • code
  • 89.05 %
  • assert
  • 95.97 %
  • func
  • 77.74 %
  • block
  • 95.94 %
  • line
  • 96.87 %
  • branch
  • 89.66 %
  • toggle
  • 79.18 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 30.480us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 44.927us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.468us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 40.504us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.049us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 30.929us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 16.468us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 234.343us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 13.554us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 669.054us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 7.000s 372.069us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 8.000s 1781.168us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.000s 5279.223us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 378.658us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 142.663us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 1764.390us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 1102.134us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 52.225us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 1186.559us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 89.716us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 17.000s 4379.945us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 18.119us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10800.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 36.101us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 84.039us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 84.039us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 44.927us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.468us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.049us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 45.319us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 44.927us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.468us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.049us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 45.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 900.158us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 318.589us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 318.589us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 234.343us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 900.158us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 900.158us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 900.158us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 900.158us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 900.158us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 900.158us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 900.158us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 900.158us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 669.054us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 6559.291us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 439.996us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 439.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 47610749815915358465261551635996922690539119809404668815898250577039980847803 None
lc_ctrl_state_post_trans 83946811794685936262314641608048113519426686454810668296213323142014768911754 None
lc_ctrl_prog_failure 100555549461941248097142298479253264198763454790513862433412762665326368590332 None
lc_ctrl_errors 13163240480708577741507086891804036073389901827080015377114664985030085514121 None
lc_ctrl_jtag_state_failure 7734046008642381579592080579538751761797078961883953411025110309750320356761 None
lc_ctrl_jtag_state_post_trans 38970007484452949414741564530900618444680788554365601362057415992560861611336 None
lc_ctrl_jtag_prog_failure 77525053182375322506680732430298449108090472974544445682295479469057771018367 None
lc_ctrl_jtag_errors 10230395561299221344942936181548740617759551074623563296210950429784816630505 None
lc_ctrl_sec_mubi 22778754740416141269340186956531901949716408988706746169267773191246254016768 None
lc_ctrl_stress_all 48981598553462019717997229448398938420514234445889142999489214555070905687732 None
lc_ctrl_stress_all_with_rand_reset 56069874962245414828111770910914424801207461387102389946332015792354463193194 None