Simulation Results: lc_ctrl/volatile_unlock_enabled

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.89 %
  • code
  • 90.81 %
  • assert
  • 96.83 %
  • func
  • 79.03 %
  • block
  • 96.57 %
  • line
  • 97.39 %
  • branch
  • 91.30 %
  • toggle
  • 79.33 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
73.33%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 23.645us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 22.881us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 57.231us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 214.436us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 18.811us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 308.931us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 57.231us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 18.811us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 1633.150us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 56.874us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 2 7 28.57
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 296.876us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 21.000s 22257.422us 1 1 100.00
jtag_access 11 13 84.62
lc_ctrl_jtag_smoke 5.000s 1561.205us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 21.000s 22257.422us 1 1 100.00
lc_ctrl_jtag_access 6.000s 322.730us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 1977.332us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 72.579us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 75.044us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.000s 1802.415us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 1478.726us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 97.145us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 522.152us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 46.165us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 371.029us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 43.531us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10800.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 56.440us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 199.774us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 199.774us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 22.881us 1 1 100.00
lc_ctrl_csr_rw 2.000s 57.231us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 18.811us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 53.838us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 22.881us 1 1 100.00
lc_ctrl_csr_rw 2.000s 57.231us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 18.811us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 53.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 428.586us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 450.388us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 450.388us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 1633.150us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 428.586us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 428.586us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 428.586us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 428.586us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 428.586us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 428.586us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 428.586us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 428.586us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 296.876us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 1102.221us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 400.263us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 400.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
lc_ctrl_state_failure 39004319007528455319780044123820118959639353197925841701463676290273217734037 None
lc_ctrl_state_post_trans 17721844493491699863185514355908549842697397944635680403827808822032534397701 None
lc_ctrl_prog_failure 25167517780049433534623539332723992692735523440844072839270395132475693792495 None
lc_ctrl_errors 73506383718596831681257570720392333328025586217429255499161914593388542370532 None
lc_ctrl_jtag_state_failure 62036291709713070691933834800228329917674074877831486023731869605151343674522 None
lc_ctrl_jtag_state_post_trans 15005856565641776015632659854847106107447673990332354426203254614604184913437 None
lc_ctrl_jtag_prog_failure 67061713318065096527105932560704878986153174543744537517086197854839094686920 None
lc_ctrl_sec_mubi 76405358214849133482057339548589814323838212070676320931382285914921980285093 None
lc_ctrl_stress_all 107811011775394630651163243426309146834450661662190387538315021632061537398231 None
lc_ctrl_stress_all_with_rand_reset 68033879218458479490445217589414740237584433279477882741934200536559678915230 None