Simulation Results: mbx

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.48 %
  • code
  • 87.88 %
  • assert
  • 97.53 %
  • func
  • 77.04 %
  • block
  • 95.99 %
  • line
  • 95.47 %
  • branch
  • 89.37 %
  • toggle
  • 78.80 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 97.000s 26206.384us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 20.746us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 13.939us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 5.000s 1000.762us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 31.564us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 1.476us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 13.939us 1 1 100.00
mbx_csr_aliasing 1.000s 31.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 3.000s 21.851us 0 1 0.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 191.000s 27104.933us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 18.000s 13420.683us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 11.000s 1014.799us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 20.173us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 30.841us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 17.191us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 17.191us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 20.746us 1 1 100.00
mbx_csr_rw 2.000s 13.939us 1 1 100.00
mbx_csr_aliasing 1.000s 31.564us 1 1 100.00
mbx_same_csr_outstanding 2.000s 40.049us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 20.746us 1 1 100.00
mbx_csr_rw 2.000s 13.939us 1 1 100.00
mbx_csr_aliasing 1.000s 31.564us 1 1 100.00
mbx_same_csr_outstanding 2.000s 40.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 152.366us 1 1 100.00
mbx_sec_cm 2.000s 12.716us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:696) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 641928411828579275510807784813193678347485135371026707021054588910252057011 85
TL item was: req: (cip_tl_seq_item@22645) { a_addr: 'h1ca3cf70 a_data: 'h50991d0f a_mask: 'ha a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h1 a_user: 'h241f0 d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 17191105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 110726074681988826040940184261412401173749517898768653171293795363594776425494 86
TL item was: req: (cip_tl_seq_item@20607) { a_addr: 'h8cc489b0 a_data: 'hfbed364c a_mask: 'h6 a_size: 'h2 a_param: 'h0 a_source: 'h98 a_opcode: 'h1 a_user: 'h24eed d_param: 'h0 d_source: 'h98 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1476162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed 1 test run
mbx_stress 23409815646078243697261193198530904700055158628344000432895782029416198850790 226
UVM_ERROR @ 21850693 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 21850693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---