Simulation Results: otbn

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.77 %
  • code
  • 81.77 %
  • assert
  • 89.66 %
  • func
  • 97.88 %
  • block
  • 97.71 %
  • line
  • 97.94 %
  • branch
  • 81.66 %
  • toggle
  • 81.26 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 14.000s 44.422us 1 1 100.00
otbn_smoke_vectorized 11.000s 21.132us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 122.009us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 15.539us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 39.122us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 335.675us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 30.592us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 151.948us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 39.122us 1 1 100.00
otbn_csr_aliasing 5.000s 30.592us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 71.000s 776.397us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 68.000s 1113.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 60.000s 269.637us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 82.000s 1771.388us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 256.000s 3901.050us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 19.000s 66.395us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 14.000s 122.113us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 27.035us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 14.936us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 63.978us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 12.959us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 81.127us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 81.127us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 15.539us 1 1 100.00
otbn_csr_rw 5.000s 39.122us 1 1 100.00
otbn_csr_aliasing 5.000s 30.592us 1 1 100.00
otbn_same_csr_outstanding 4.000s 42.466us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 15.539us 1 1 100.00
otbn_csr_rw 5.000s 39.122us 1 1 100.00
otbn_csr_aliasing 5.000s 30.592us 1 1 100.00
otbn_same_csr_outstanding 4.000s 42.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 89.406us 1 1 100.00
otbn_dmem_err 13.000s 24.595us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 17.000s 120.086us 1 1 100.00
otbn_controller_ispr_rdata_err 11.000s 231.372us 1 1 100.00
otbn_mac_bignum_acc_err 10.000s 51.794us 1 1 100.00
otbn_urnd_err 7.000s 115.552us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 44.860us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 10.000s 21.865us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 45.050us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
otbn_tl_intg_err 30.000s 357.029us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 66.000s 611.647us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 14.000s 44.422us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 13.000s 24.595us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 89.406us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 30.000s 357.029us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 14.000s 122.113us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 89.406us 1 1 100.00
otbn_dmem_err 13.000s 24.595us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 27.035us 1 1 100.00
otbn_illegal_mem_acc 8.000s 44.860us 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 122.009us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 89.406us 1 1 100.00
otbn_dmem_err 13.000s 24.595us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 27.035us 1 1 100.00
otbn_illegal_mem_acc 8.000s 44.860us 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 14.000s 122.113us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 89.406us 1 1 100.00
otbn_dmem_err 13.000s 24.595us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 27.035us 1 1 100.00
otbn_illegal_mem_acc 8.000s 44.860us 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 122.009us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 10.000s 68.089us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 94.017us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 41.000s 170.901us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 41.000s 170.901us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 17.000s 30.501us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 16.000s 73.997us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 57.154us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 57.154us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 9.000s 15.036us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 122.009us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 122.009us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 122.009us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 256.000s 3901.050us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 122.009us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 122.009us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 26.000s 65.759us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 122.009us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 546.000s 6608.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 52.000s 570.317us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 56745835359999163797796183740959201995145799891052568064701026953917626161407 164
UVM_INFO @ 570316961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 90278426794153089113407014912338699774538251416119162933214889984833299096717 114
UVM_ERROR @ 115551889 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 115551889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---