Simulation Results: otp_ctrl

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.61 %
  • code
  • 72.35 %
  • assert
  • 91.82 %
  • func
  • 56.67 %
  • line
  • 87.36 %
  • branch
  • 83.48 %
  • cond
  • 86.96 %
  • toggle
  • 67.60 %
  • FSM
  • 36.37 %
Validation stages
V1
88.89%
V2
75.00%
V2S
55.56%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.380s 54.397us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 7.220s 422.583us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.280s 85.717us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 3.020s 92.380us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.610s 689.202us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.070s 180.908us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.990s 243.777us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 3.020s 92.380us 1 1 100.00
otp_ctrl_csr_aliasing 4.070s 180.908us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.090s 44.959us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.150s 44.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 164.160s 16491.508us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.900s 84.409us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 24.910s 3625.522us 1 1 100.00
otp_ctrl_check_fail 3.830s 203.783us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.070s 620.909us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 11.190s 864.572us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 6.130s 333.772us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 49.650s 15300.766us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 38.550s 855.440us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 37.250s 2879.269us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 18.800s 1522.919us 0 1 0.00
stress_all 1 1 100.00
otp_ctrl_stress_all 24.700s 1313.950us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.460s 170.242us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.740s 107.123us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 7.250s 389.077us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 7.250s 389.077us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.280s 85.717us 1 1 100.00
otp_ctrl_csr_rw 3.020s 92.380us 1 1 100.00
otp_ctrl_csr_aliasing 4.070s 180.908us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.610s 309.729us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.280s 85.717us 1 1 100.00
otp_ctrl_csr_rw 3.020s 92.380us 1 1 100.00
otp_ctrl_csr_aliasing 4.070s 180.908us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.610s 309.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
otp_ctrl_tl_intg_err 15.420s 777.853us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 15.420s 777.853us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 7.220s 422.583us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 7.220s 422.583us 0 1 0.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
otp_ctrl_macro_errs 37.250s 2879.269us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
otp_ctrl_macro_errs 37.250s 2879.269us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.500s 2807.676us 1 1 100.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.900s 84.409us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.830s 203.783us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 11.190s 864.572us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 11.190s 864.572us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 11.190s 864.572us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 11.190s 864.572us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 11.190s 864.572us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 7.220s 422.583us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 11.190s 864.572us 1 1 100.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 7.220s 422.583us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 506.310s 200000.000us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.070s 620.909us 1 1 100.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 7.220s 422.583us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 7.220s 422.583us 0 1 0.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 37.250s 2879.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 196.950s 62927.836us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 67.340s 3183.177us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_smoke 52513066197257238056851609798974059513940735728790495703304885997538789440924 4150
UVM_INFO @ 422583100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 25088838586016178899297689643453523837036424246416119475357084291484358147612 683
UVM_INFO @ 84408951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_parallel_key_req 46387117600079722348345166063461580130711766354424991354442002765011261010355 1990
UVM_INFO @ 333771882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 2684845206843993074431411437807253168716091015317080916327788932233149439917 9091
UVM_INFO @ 1522918849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 9488229195861301621544541197318024628580128479072660360366984027829805492370 112803
UVM_INFO @ 16491508121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 46266825869937169049439032264492092859770990723009835135491582280144599380064 95
UVM_INFO @ 62927835542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 51967197699794150270306492305511434054174577367075674820062763932127375999102 1086
UVM_INFO @ 203782620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
otp_ctrl_sec_cm 45888795394392040773176815218830631936543808691281760644561008180864328625746 2385
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---