Simulation Results: rstmgr

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 99.04 %
  • assert
  • 98.35 %
  • func
  • 95.18 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.86 %
  • toggle
  • 98.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.640s 59.054us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.710s 92.768us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.180s 36.894us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.630s 63.053us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.120s 35.894us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.590s 97.705us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.180s 36.894us 1 1 100.00
rstmgr_csr_aliasing 1.120s 35.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.670s 86.093us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.500s 44.224us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.600s 66.360us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.920s 506.617us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.920s 506.617us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.920s 506.617us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.920s 506.617us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 29.040s 3734.397us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.070s 35.933us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.900s 39.723us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.900s 39.723us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.710s 92.768us 1 1 100.00
rstmgr_csr_rw 1.180s 36.894us 1 1 100.00
rstmgr_csr_aliasing 1.120s 35.894us 1 1 100.00
rstmgr_same_csr_outstanding 1.320s 38.827us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.710s 92.768us 1 1 100.00
rstmgr_csr_rw 1.180s 36.894us 1 1 100.00
rstmgr_csr_aliasing 1.120s 35.894us 1 1 100.00
rstmgr_same_csr_outstanding 1.320s 38.827us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 28.780s 3435.908us 1 1 100.00
rstmgr_tl_intg_err 6.660s 622.933us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 28.780s 3435.908us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 28.780s 3435.908us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 6.660s 622.933us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.610s 61.192us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 0 1 0.00
rstmgr_leaf_rst_cnsty 1.310s 30.234us 0 1 0.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.630s 291.930us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 28.780s 3435.908us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.180s 36.894us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.180s 36.894us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_cnsty_fault. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rstmgr_leaf_rst_cnsty 89921919444992366952057366457479884835848066415658805752552360113674844598813 85
UVM_INFO @ 30233696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---