Simulation Results

Simulation Results: rv_dm/use_dmi_interface

26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
90.69 %

code
81.20 %

assert
96.66 %

func
94.20 %

block
92.24 %

line
92.90 %

branch
78.90 %

toggle
72.64 %

FSM
80.36 %

Validation stages

V1		92.59%
V2		73.91%
V2S		100.00%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	51.000s	1437.198us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	51.000s	263.571us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	39.000s	225.412us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	43.000s	4408.709us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	52.000s	127.496us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	46.000s	2213.269us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	34.000s	2219.085us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	59.000s	16536.575us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	53.000s	8465.105us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	55.000s	1205.771us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	37.000s	364.493us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	36.000s	847.696us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	46.000s	206.629us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	51.000s	118.706us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	42.000s	2703.052us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	38.000s	112.620us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	52.000s	1398.112us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	55.000s	1205.771us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	36.000s	329.540us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	48.000s	244.473us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	36.000s	847.696us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	44.000s	67.956us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	51.000s	467.873us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	46.000s	127.060us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	87.000s	41748.809us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	52.000s	862.556us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	47.000s	164.765us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	52.000s	862.556us	1	1	100.00
	rv_dm_csr_rw	46.000s	127.060us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	50.000s	40.237us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	47.000s	67.601us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	51.000s	1437.198us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	53.000s	775.494us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	48.000s	185.125us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	40.000s	619.896us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	42.000s	928.812us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	59.000s	4702.536us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	50.000s	90.390us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	50.000s	5812.565us	0	1	0.00
sba_autoincrement				1	1	100.00
	rv_dm_autoincr_sba_tl_access	101.000s	51542.214us	1	1	100.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	42.000s	272.955us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	52.000s	1736.250us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	45.000s	297.152us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	44.000s	268.712us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	79.000s	14927.135us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	91.000s	2104.942us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	41.000s	136.978us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	8350.000s	10000000.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	43.000s	107.724us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	47.000s	431.379us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	47.000s	431.379us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	52.000s	862.556us	1	1	100.00
	rv_dm_csr_hw_reset	51.000s	467.873us	1	1	100.00
	rv_dm_csr_rw	46.000s	127.060us	1	1	100.00
	rv_dm_same_csr_outstanding	48.000s	330.258us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	52.000s	862.556us	1	1	100.00
	rv_dm_csr_hw_reset	51.000s	467.873us	1	1	100.00
	rv_dm_csr_rw	46.000s	127.060us	1	1	100.00
	rv_dm_same_csr_outstanding	48.000s	330.258us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	46.000s	259.851us	1	1	100.00
	rv_dm_tl_intg_err	52.000s	1231.076us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	52.000s	1231.076us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	52.000s	1736.250us	1	1	100.00
	rv_dm_debug_disabled	51.000s	94.439us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	52.000s	1736.250us	1	1	100.00
	rv_dm_debug_disabled	51.000s	94.439us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	51.000s	1437.198us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	46.000s	203.677us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	45.000s	195.808us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	45.000s	195.808us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	46.000s	203.677us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	45.000s	611.126us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	151.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	5917154036411983417771530287585817023719676533275435018770439522718597897418	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23822
	rv_dm_bad_sba_tl_access	103721956020123019340697915947179470604273017897553337227936274395513014463027	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24117
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	82090152995950402283026127488546741663458712761406050187518403545494955040606	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	5539053660284464808779343971712203462308936051048519403434075458354680559791	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	50955925173052337260119454349053136530099643114145206934121846933786169650966	107	UVM_INFO @ 90389645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	27357969476291248922332864162190266144241903120707835778994170350947741456100	87	UVM_INFO @ 206629016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	2401333944299000338981265543538916668592238049002662900350146430528791003956	87	UVM_INFO @ 268711705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	108063366791018901779801457400605947465768671576219816524496192765713429987506	87	UVM_INFO @ 272954904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23873) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	23513287255145489270623576465227475119790458922301754522607003280105711487727	87	). UVM_INFO @ 67955831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [rv_dm_common_vseq] Check failed (vseq_done)				1 test run
	rv_dm_stress_all_with_rand_reset	71701520711068294743220424364166557675877045795829304918398643043790934381611	95	UVM_INFO @ 611125877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---