Simulation Results: rv_timer

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 90.45 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 500.846us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 173.617us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 13.287us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 4.000s 345.908us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 14.327us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 74.171us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 13.287us 1 1 100.00
rv_timer_csr_aliasing 1.000s 14.327us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 451.449us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 1384.454us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 1.000s 118.239us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 1.000s 118.239us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 12.000s 4786.075us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 12.668us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 38.564us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 413.560us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 413.560us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 173.617us 1 1 100.00
rv_timer_csr_rw 1.000s 13.287us 1 1 100.00
rv_timer_csr_aliasing 1.000s 14.327us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 92.272us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 173.617us 1 1 100.00
rv_timer_csr_rw 1.000s 13.287us 1 1 100.00
rv_timer_csr_aliasing 1.000s 14.327us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 92.272us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 164.646us 1 1 100.00
rv_timer_tl_intg_err 2.000s 391.908us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 391.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 1.000s 32.262us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 1.000s 171.689us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 56.000s 24818.657us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 35109045671357850601010489780052605273145562412994749202232771756845988954576 85
UVM_INFO @ 171688988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---