Simulation Results: spi_host

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.88 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 35.000s 1000.133us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 20.967us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 44.960us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 5.000s 1617.365us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 42.613us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 50.990us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 44.960us 1 1 100.00
spi_host_csr_aliasing 1.000s 42.613us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 24.394us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 104.685us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 22.615us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 115.578us 1 1 100.00
spi_host_error_cmd 1.000s 47.709us 1 1 100.00
spi_host_event 16.000s 13220.592us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 63.693us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 63.693us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 63.693us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 321.000s 15279.966us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 51.795us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 33.467us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 63.693us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 63.693us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 35.000s 1000.133us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 35.000s 1000.133us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 268.699us 1 1 100.00
spien 1 1 100.00
spi_host_spien 10.000s 887.046us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 41.000s 2478.654us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 5.000s 1678.332us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 115.578us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 40.879us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 156.234us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 91.419us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 91.419us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 20.967us 1 1 100.00
spi_host_csr_rw 1.000s 44.960us 1 1 100.00
spi_host_csr_aliasing 1.000s 42.613us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 24.886us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 20.967us 1 1 100.00
spi_host_csr_rw 1.000s 44.960us 1 1 100.00
spi_host_csr_aliasing 1.000s 42.613us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 24.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 113.503us 1 1 100.00
spi_host_sec_cm 1.000s 143.160us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 113.503us 1 1 100.00