Simulation Results: sram_ctrl/main

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.52 %
  • code
  • 94.32 %
  • assert
  • 97.83 %
  • func
  • 94.40 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 90.91 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 741.557us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 47.138us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 48.683us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 665.294us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 41.974us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 375.307us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 48.683us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 41.974us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 327.000s 103167.597us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 97.000s 1611.061us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 39.000s 10320.338us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 244.000s 5717.805us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 221.000s 27344.609us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 20.000s 38919.863us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 60.000s 53533.863us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 22.000s 2396.414us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.000s 1128.748us 1 1 100.00
sram_ctrl_partial_access_b2b 386.000s 152729.337us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 1431.744us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 1032.292us 1 1 100.00
sram_ctrl_throughput_w_readback 6.000s 5577.029us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 500.373us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 5.000s 867.148us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 327.000s 34234.238us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 11.464us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 152.977us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 152.977us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 47.138us 1 1 100.00
sram_ctrl_csr_rw 1.000s 48.683us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 41.974us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.778us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 47.138us 1 1 100.00
sram_ctrl_csr_rw 1.000s 48.683us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 41.974us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.778us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 10892.013us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 416.624us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 338.783us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 416.624us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 338.783us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 500.373us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 500.373us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 48.683us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 22.000s 2396.414us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 22.000s 2396.414us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 22.000s 2396.414us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 60.000s 53533.863us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 10892.013us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 741.557us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 741.557us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 22.000s 2396.414us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 416.624us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 60.000s 53533.863us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 416.624us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 416.624us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 741.557us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 416.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 39.000s 1977.284us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 26746516561200993925302812978087957940538577332111845390384028471999910491045 None
sram_ctrl_mubi_enc_err 95475287671651025955184517165978113106907413568743069974031329265931316018152 None