Simulation Results: sram_ctrl/ret

 
26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.70 %
  • code
  • 81.69 %
  • assert
  • 97.81 %
  • func
  • 92.60 %
  • block
  • 92.12 %
  • line
  • 93.71 %
  • branch
  • 88.07 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 115.703us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 15.741us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 34.792us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 413.562us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 10.675us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 38.829us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 34.792us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 10.675us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 829.944us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 384.476us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 560.131us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 149.000s 2129.639us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 8.000s 1174.646us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 4.000s 654.824us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 601.893us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 284.867us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 357.071us 1 1 100.00
sram_ctrl_partial_access_b2b 257.000s 10129.002us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 111.237us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 239.243us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 242.090us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 700.683us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 31.028us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 17.000s 2090.237us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 13.692us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 55.455us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 55.455us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 15.741us 1 1 100.00
sram_ctrl_csr_rw 2.000s 34.792us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 10.675us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 74.937us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 15.741us 1 1 100.00
sram_ctrl_csr_rw 2.000s 34.792us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 10.675us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 74.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1629.621us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 723.959us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 281.768us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 723.959us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 281.768us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 700.683us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 700.683us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 34.792us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 284.867us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 284.867us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 284.867us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 601.893us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1629.621us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 115.703us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 115.703us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 284.867us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 723.959us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 601.893us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 723.959us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 723.959us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 115.703us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 723.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 11.000s 573.834us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 1622614601881614463344578451954907204350163512828510892839938055620982139844 None
sram_ctrl_mubi_enc_err 7549712659903169735894772604991994448992529396376171418317245323638236328806 None
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 114961284677711882936116122896248140170963565216613337136494489879644967592842 98
UVM_INFO @ 38829125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---