Simulation Results

Simulation Results: uart

26/08/2026 21:26:37 DVSim: v1.52.0 sha: af31ff0 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.64 %

code
73.69 %

assert
98.56 %

func
90.69 %

block
98.66 %

line
99.24 %

branch
97.42 %

toggle
73.08 %

FSM
25.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	4.000s	529.203us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	2.000s	16.220us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	1.000s	12.924us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	4.000s	161.429us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	2.000s	21.681us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	1.000s	24.644us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	1.000s	12.924us	1	1	100.00
	uart_csr_aliasing	2.000s	21.681us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	21.000s	32868.861us	1	1	100.00
parity				2	2	100.00
	uart_smoke	4.000s	529.203us	1	1	100.00
	uart_tx_rx	21.000s	32868.861us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	384.000s	197601.101us	1	1	100.00
	uart_rx_parity_err	53.000s	25560.335us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	21.000s	32868.861us	1	1	100.00
	uart_intr	384.000s	197601.101us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	78.000s	37118.090us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	12.000s	30284.314us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	105.000s	131872.968us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	384.000s	197601.101us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	384.000s	197601.101us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	384.000s	197601.101us	1	1	100.00
perf				1	1	100.00
	uart_perf	177.000s	23010.101us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	2.000s	518.345us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	2.000s	518.345us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	3.000s	1094.388us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	8.000s	2696.377us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	4.000s	2057.853us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	14.000s	3866.878us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	254.000s	162234.484us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	56.000s	67202.186us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	2.000s	32.845us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	2.000s	54.692us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	2.000s	117.379us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	2.000s	117.379us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	2.000s	16.220us	1	1	100.00
	uart_csr_rw	1.000s	12.924us	1	1	100.00
	uart_csr_aliasing	2.000s	21.681us	1	1	100.00
	uart_same_csr_outstanding	1.000s	31.366us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	2.000s	16.220us	1	1	100.00
	uart_csr_rw	1.000s	12.924us	1	1	100.00
	uart_csr_aliasing	2.000s	21.681us	1	1	100.00
	uart_same_csr_outstanding	1.000s	31.366us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	133.733us	1	1	100.00
	uart_tl_intg_err	2.000s	588.388us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	2.000s	588.388us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	19.000s	3387.226us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:376) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *				1 test run
	uart_noise_filter	102790793814053415983406896076326973861890012795889373906461290750990049257186	83	UVM_ERROR @ 281827966 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 285393162 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 285393162 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 294567020 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0