Simulation Results: ac_range_check

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.88 %
  • code
  • 93.06 %
  • assert
  • 97.75 %
  • func
  • 57.84 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 35.000s 21163.687us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 59.000s 9534.847us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 10.000s 121.780us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 10.000s 64.555us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 35.000s 2825.883us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1078.235us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 10.000s 60.447us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 10.000s 64.555us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1078.235us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 11.000s 151.683us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 48.000s 6221.875us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 191.000s 5899.194us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 9.000s 19.485us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 9.000s 14.996us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 5.000s 89.585us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 5.000s 89.585us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 121.780us 1 1 100.00
ac_range_check_csr_rw 10.000s 64.555us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1078.235us 1 1 100.00
ac_range_check_same_csr_outstanding 10.000s 53.256us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 121.780us 1 1 100.00
ac_range_check_csr_rw 10.000s 64.555us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1078.235us 1 1 100.00
ac_range_check_same_csr_outstanding 10.000s 53.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 20.000s 1553.661us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 20.000s 1553.661us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 20.000s 1553.661us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 20.000s 1553.661us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 79.000s 1382.706us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 9.000s 12.696us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 693.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 348.000s 6130.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 33.000s 1252.635us 1 1 100.00