Simulation Results: aes/gcm_unmasked

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.45 %
  • code
  • 90.16 %
  • assert
  • 97.75 %
  • func
  • 65.43 %
  • block
  • 89.87 %
  • line
  • 92.04 %
  • branch
  • 81.94 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 58.280us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 119.774us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 72.638us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 61.955us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 1713.360us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 63.413us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 74.213us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 61.955us 1 1 100.00
aes_csr_aliasing 2.000s 63.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 119.774us 1 1 100.00
aes_config_error 3.000s 275.888us 1 1 100.00
aes_stress 3.000s 206.820us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 119.774us 1 1 100.00
aes_config_error 3.000s 275.888us 1 1 100.00
aes_stress 3.000s 206.820us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 206.820us 1 1 100.00
aes_b2b 2.000s 56.980us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 206.820us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 119.774us 1 1 100.00
aes_config_error 3.000s 275.888us 1 1 100.00
aes_stress 3.000s 206.820us 1 1 100.00
aes_alert_reset 3.000s 72.000us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 62.836us 1 1 100.00
aes_config_error 3.000s 275.888us 1 1 100.00
aes_alert_reset 3.000s 72.000us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 110.907us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 315.165us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 72.000us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 206.820us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 206.820us 1 1 100.00
aes_sideload 4.000s 176.674us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 129.194us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 8.000s 321.014us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 64.949us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 115.652us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 115.652us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 72.638us 1 1 100.00
aes_csr_rw 1.000s 61.955us 1 1 100.00
aes_csr_aliasing 2.000s 63.413us 1 1 100.00
aes_same_csr_outstanding 2.000s 139.706us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 72.638us 1 1 100.00
aes_csr_rw 1.000s 61.955us 1 1 100.00
aes_csr_aliasing 2.000s 63.413us 1 1 100.00
aes_same_csr_outstanding 2.000s 139.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 231.393us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 75.284us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 232.557us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 232.557us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 232.557us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 232.557us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 286.354us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 861.392us 1 1 100.00
aes_tl_intg_err 2.000s 185.982us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 185.982us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 72.000us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 232.557us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 232.557us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 119.774us 1 1 100.00
aes_stress 3.000s 206.820us 1 1 100.00
aes_alert_reset 3.000s 72.000us 1 1 100.00
aes_core_fi 3602.196s 0.000us 0 1 0.00
sec_cm_gcm_config_sparse 2 3 66.67
aes_config_error 3.000s 275.888us 1 1 100.00
aes_stress 3.000s 206.820us 1 1 100.00
aes_core_fi 3602.196s 0.000us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 232.557us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 70.156us 1 1 100.00
aes_stress 3.000s 206.820us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 206.820us 1 1 100.00
aes_sideload 4.000s 176.674us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 70.156us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 70.156us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 70.156us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 70.156us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 70.156us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 206.820us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 206.820us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 75.284us 1 1 100.00
aes_ctr_fi 2.000s 49.206us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 75.284us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 75.284us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 49.206us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 75.284us 1 1 100.00
aes_ctr_fi 2.000s 49.206us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 72.000us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 75.284us 1 1 100.00
aes_ctr_fi 2.000s 49.206us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 75.284us 1 1 100.00
aes_ctr_fi 2.000s 49.206us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 49.206us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 75.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 10.000s 1730.095us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
aes_fi 90715267532085347403441482787016634299348074493619672256905096611053696290286 None
aes_control_fi 4788698872028785032244541905934052790010049891953815032063771881392209970230 None
aes_core_fi 89763576954100177222499886723876814445216212862862811679805177809127473173086 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 82579145852195241447774641134682024791851700003122155717427239934920043141541 2266
UVM_INFO @ 231392541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 115733270917659441974387051102934312018972016041098830806800670509845123628841 484
UVM_INFO @ 1730095292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---