Simulation Results: alert_handler

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.06 %
  • code
  • 90.11 %
  • assert
  • 98.20 %
  • func
  • 81.86 %
  • line
  • 99.69 %
  • branch
  • 98.38 %
  • cond
  • 92.38 %
  • toggle
  • 87.54 %
  • FSM
  • 72.58 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 8.710s 93.114us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.370s 135.686us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.930s 46.371us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 382.620s 31665.320us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 73.910s 1071.513us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.540s 106.846us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.930s 46.371us 1 1 100.00
alert_handler_csr_aliasing 73.910s 1071.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 271.790s 4731.601us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 64.940s 2412.565us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 3198.460s 64478.482us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 22.090s 6300.613us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 8.710s 93.114us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 18.300s 304.694us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 11.510s 611.840us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 229.910s 5591.709us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1616.740s 126652.721us 1 1 100.00
alert_handler_lpg_stub_clk 2919.970s 57287.126us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 183.810s 7535.138us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.280s 127.014us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 5.110s 243.595us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.080s 10.792us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 21.560s 301.817us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 21.560s 301.817us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.370s 135.686us 1 1 100.00
alert_handler_csr_rw 4.930s 46.371us 1 1 100.00
alert_handler_csr_aliasing 73.910s 1071.513us 1 1 100.00
alert_handler_same_csr_outstanding 25.940s 660.111us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.370s 135.686us 1 1 100.00
alert_handler_csr_rw 4.930s 46.371us 1 1 100.00
alert_handler_csr_aliasing 73.910s 1071.513us 1 1 100.00
alert_handler_same_csr_outstanding 25.940s 660.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 189.180s 7216.844us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 189.180s 7216.844us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 189.180s 7216.844us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 189.180s 7216.844us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 625.660s 5386.586us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 10.100s 363.648us 1 1 100.00
alert_handler_tl_intg_err 28.200s 215.287us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 28.200s 215.287us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 189.180s 7216.844us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 8.710s 93.114us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 8.710s 93.114us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 8.710s 93.114us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 8.710s 93.114us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 22.090s 6300.613us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1616.740s 126652.721us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 22.090s 6300.613us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3198.460s 64478.482us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3198.460s 64478.482us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.100s 363.648us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.100s 363.648us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.100s 363.648us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.100s 363.648us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 10.100s 363.648us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.100s 363.648us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.100s 363.648us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.100s 363.648us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 10.100s 363.648us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 155.340s 4219.645us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 25565113398211003719546619072713097975924096830739397943116144259335650251399 154
UVM_INFO @ 127013996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 11732320611779437196415011198547487276026636410705949341244607100343370930989 128
UVM_INFO @ 4219645324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---