Simulation Results: clkmgr

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.93 %
  • code
  • 69.78 %
  • assert
  • 90.50 %
  • func
  • 61.52 %
  • line
  • 82.27 %
  • branch
  • 87.53 %
  • cond
  • 79.11 %
  • toggle
  • 100.00 %
  • FSM
  • 0.00 %
Validation stages
V1
83.33%
V2
69.23%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.700s 58.063us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.540s 53.848us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 3.430s 189.897us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 3.060s 168.855us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.080s 41.525us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.610s 111.091us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 3.430s 189.897us 1 1 100.00
clkmgr_csr_aliasing 1.080s 41.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.110s 24.596us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.360s 62.834us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.190s 32.550us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.700s 58.063us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 1.050s 6.508us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 1.010s 7.962us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 1.050s 6.508us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.460s 60.038us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.930s 16.503us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 5.850s 389.121us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 5.850s 389.121us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 1.540s 53.848us 1 1 100.00
clkmgr_csr_rw 3.430s 189.897us 1 1 100.00
clkmgr_csr_aliasing 1.080s 41.525us 1 1 100.00
clkmgr_same_csr_outstanding 0.880s 11.329us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 1.540s 53.848us 1 1 100.00
clkmgr_csr_rw 3.430s 189.897us 1 1 100.00
clkmgr_csr_aliasing 1.080s 41.525us 1 1 100.00
clkmgr_same_csr_outstanding 0.880s 11.329us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 4.960s 328.142us 1 1 100.00
clkmgr_tl_intg_err 1.040s 6.656us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.540s 58.797us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.540s 58.797us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.540s 58.797us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.540s 58.797us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.020s 8.893us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.040s 6.656us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 1.050s 6.508us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 1.010s 7.962us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.540s 58.797us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.420s 30.534us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 3.430s 189.897us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 4.960s 328.142us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 3.430s 189.897us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 3.430s 189.897us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 4.960s 328.142us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.930s 4.102us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.110s 8.510us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 70266734296853142798577966894317014301649039898886437740549331222430207003273 82
UVM_INFO @ 6508345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 10522109009032592633608324395145730210896665920472062540607957569851527598042 84
UVM_INFO @ 8510369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 54413161952022381663235968618060173463695296737172659344234575305804755432104 83
UVM_INFO @ 7961588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 21791920751940688725792564898797239119532995098835999199823507150566842162164 84
UVM_INFO @ 60037693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 62798670637000301903978016907093223492629882038546290126132922975564407842021 81
UVM_INFO @ 8892526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 42381446636875678001581133427886134808078447436342725113824993141556359829301 92
UVM_INFO @ 6656398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 53877693725092953821234017090697821514755064784086134270522996152211296022862 80
UVM_INFO @ 4101709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 179424412286363702969258311423786699733024430722001174249332026810854081802 81
UVM_INFO @ 168855078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 21861132796265414024003838895933180762136317800320550053077246580393615742136 81
UVM_INFO @ 11329412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---