Simulation Results: dma

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.66 %
  • code
  • 90.73 %
  • assert
  • 96.61 %
  • func
  • 60.62 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 757.307us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 313.667us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 806.194us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 14.480us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 27.217us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 3472.942us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 53.024us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 72.790us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 27.217us 1 1 100.00
dma_csr_aliasing 2.000s 53.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 132.000s 30318.865us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 352.000s 23248.281us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 342.000s 25732.598us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 342.000s 25732.598us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 352.000s 23248.281us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 489.000s 77165.888us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 342.000s 25732.598us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 10.000s 776.377us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 242.000s 25185.310us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 13.072us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 83.173us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 137.771us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 137.771us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 14.480us 1 1 100.00
dma_csr_rw 1.000s 27.217us 1 1 100.00
dma_csr_aliasing 2.000s 53.024us 1 1 100.00
dma_same_csr_outstanding 2.000s 204.741us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 14.480us 1 1 100.00
dma_csr_rw 1.000s 27.217us 1 1 100.00
dma_csr_aliasing 2.000s 53.024us 1 1 100.00
dma_same_csr_outstanding 2.000s 204.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 10.000s 235.880us 1 1 100.00
dma_generic_stress 489.000s 77165.888us 1 1 100.00
dma_handshake_stress 342.000s 25732.598us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 1307.993us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 5.000s 424.690us 1 1 100.00
dma_sec_cm 1.000s 40.275us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 106.000s 35376.500us 1 1 100.00
dma_longer_transfer 3.000s 319.180us 1 1 100.00
dma_stress_all_with_rand_reset 7.000s 256.471us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 109510599727732157218157735478591484856536411813039426498325494469356228654721 93
UVM_INFO @ 256471349ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---