Simulation Results: edn/edn0

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 75.73 %
  • code
  • 82.67 %
  • assert
  • 95.58 %
  • func
  • 48.95 %
  • block
  • 93.51 %
  • line
  • 96.49 %
  • branch
  • 86.07 %
  • toggle
  • 72.17 %
  • FSM
  • 75.97 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 24.348us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 14.320us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 62.765us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 90.528us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 79.319us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 95.412us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 62.765us 1 1 100.00
edn_csr_aliasing 2.000s 79.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 61.652us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 61.652us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 61.652us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 22.197us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 46.282us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 21.851us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 30.494us 1 1 100.00
edn_disable_auto_req_mode 2.000s 39.780us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 10.000s 548.979us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 60.580us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 45.944us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.000s 368.121us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.000s 368.121us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 14.320us 1 1 100.00
edn_csr_rw 2.000s 62.765us 1 1 100.00
edn_csr_aliasing 2.000s 79.319us 1 1 100.00
edn_same_csr_outstanding 2.000s 26.004us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 14.320us 1 1 100.00
edn_csr_rw 2.000s 62.765us 1 1 100.00
edn_csr_aliasing 2.000s 79.319us 1 1 100.00
edn_same_csr_outstanding 2.000s 26.004us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.000s 670.259us 1 1 100.00
edn_tl_intg_err 3.000s 84.119us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 29.743us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 46.282us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 670.259us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 670.259us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 670.259us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 670.259us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 46.282us 1 1 100.00
edn_sec_cm 5.000s 670.259us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 46.282us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 84.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 56.000s 8780.612us 1 1 100.00