Simulation Results: edn/edn1

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.58 %
  • code
  • 83.59 %
  • assert
  • 98.70 %
  • func
  • 80.46 %
  • line
  • 97.88 %
  • branch
  • 92.64 %
  • cond
  • 89.69 %
  • toggle
  • 95.70 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.060s 26.949us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.090s 16.953us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.160s 14.222us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.940s 554.777us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.120s 24.666us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.430s 47.689us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.160s 14.222us 1 1 100.00
edn_csr_aliasing 1.120s 24.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.700s 109.211us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.700s 109.211us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.700s 109.211us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.090s 26.493us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 40.376us 1 1 100.00
errs 1 1 100.00
edn_err 1.150s 74.893us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 21.477us 1 1 100.00
edn_disable_auto_req_mode 1.410s 61.197us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.310s 577.767us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.970s 60.540us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.070s 24.216us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.370s 400.794us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.370s 400.794us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.090s 16.953us 1 1 100.00
edn_csr_rw 1.160s 14.222us 1 1 100.00
edn_csr_aliasing 1.120s 24.666us 1 1 100.00
edn_same_csr_outstanding 1.560s 63.642us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.090s 16.953us 1 1 100.00
edn_csr_rw 1.160s 14.222us 1 1 100.00
edn_csr_aliasing 1.120s 24.666us 1 1 100.00
edn_same_csr_outstanding 1.560s 63.642us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.180s 645.665us 1 1 100.00
edn_tl_intg_err 2.150s 228.189us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.060s 15.071us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 40.376us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.180s 645.665us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.180s 645.665us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.180s 645.665us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.180s 645.665us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 40.376us 1 1 100.00
edn_sec_cm 5.180s 645.665us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 40.376us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.150s 228.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 77.900s 31812.700us 1 1 100.00