Simulation Results: hmac

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 70.02 %
  • code
  • 83.32 %
  • assert
  • 97.17 %
  • func
  • 29.56 %
  • block
  • 97.65 %
  • line
  • 98.44 %
  • branch
  • 94.11 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 19.000s 7005.286us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 19.978us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 20.008us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.000s 1373.012us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.000s 97.575us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 139.493us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 20.008us 1 1 100.00
hmac_csr_aliasing 2.000s 97.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 10.000s 207.350us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 91.000s 1869.213us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 17.000s 2631.849us 1 1 100.00
hmac_test_sha384_vectors 33.000s 2222.149us 1 1 100.00
hmac_test_sha512_vectors 29.000s 312.916us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 443.677us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 827.597us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 1863.969us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 37.000s 1666.428us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 120.000s 2645.121us 1 1 100.00
error 1 1 100.00
hmac_error 20.000s 1645.711us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 77.000s 2064.195us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 19.000s 7005.286us 1 1 100.00
hmac_long_msg 10.000s 207.350us 1 1 100.00
hmac_back_pressure 91.000s 1869.213us 1 1 100.00
hmac_datapath_stress 120.000s 2645.121us 1 1 100.00
hmac_burst_wr 37.000s 1666.428us 1 1 100.00
hmac_stress_all 1.000s 189.064us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 19.000s 7005.286us 1 1 100.00
hmac_long_msg 10.000s 207.350us 1 1 100.00
hmac_back_pressure 91.000s 1869.213us 1 1 100.00
hmac_datapath_stress 120.000s 2645.121us 1 1 100.00
hmac_wipe_secret 77.000s 2064.195us 1 1 100.00
hmac_test_sha256_vectors 17.000s 2631.849us 1 1 100.00
hmac_test_sha384_vectors 33.000s 2222.149us 1 1 100.00
hmac_test_sha512_vectors 29.000s 312.916us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 443.677us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 827.597us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 1863.969us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 19.000s 7005.286us 1 1 100.00
hmac_long_msg 10.000s 207.350us 1 1 100.00
hmac_back_pressure 91.000s 1869.213us 1 1 100.00
hmac_datapath_stress 120.000s 2645.121us 1 1 100.00
hmac_burst_wr 37.000s 1666.428us 1 1 100.00
hmac_error 20.000s 1645.711us 1 1 100.00
hmac_wipe_secret 77.000s 2064.195us 1 1 100.00
hmac_test_sha256_vectors 17.000s 2631.849us 1 1 100.00
hmac_test_sha384_vectors 33.000s 2222.149us 1 1 100.00
hmac_test_sha512_vectors 29.000s 312.916us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 443.677us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 827.597us 1 1 100.00
hmac_test_hmac512_vectors 17.000s 1863.969us 1 1 100.00
hmac_stress_all 1.000s 189.064us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1.000s 189.064us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 98.797us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 27.149us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 45.431us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 45.431us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 19.978us 1 1 100.00
hmac_csr_rw 1.000s 20.008us 1 1 100.00
hmac_csr_aliasing 2.000s 97.575us 1 1 100.00
hmac_same_csr_outstanding 2.000s 50.837us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 19.978us 1 1 100.00
hmac_csr_rw 1.000s 20.008us 1 1 100.00
hmac_csr_aliasing 2.000s 97.575us 1 1 100.00
hmac_same_csr_outstanding 2.000s 50.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 241.484us 1 1 100.00
hmac_tl_intg_err 3.000s 95.916us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 95.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 19.000s 7005.286us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 6.000s 218.583us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 314.000s 76051.620us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 63.035us 1 1 100.00