Simulation Results

Simulation Results: i2c

27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.50 %

code
85.70 %

assert
97.25 %

func
82.54 %

block
95.98 %

line
95.34 %

branch
92.78 %

toggle
72.68 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	109.000s	1402.109us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	13.000s	2924.718us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	53.074us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	80.693us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	7.000s	566.743us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	25.988us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	77.414us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	80.693us	1	1	100.00
	i2c_csr_aliasing	2.000s	25.988us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	62.776us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	2.000s	27.395us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	754.000s	3112.856us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	25.474us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3600.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	2448.000s	4205.459us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	165.018us	1	1	100.00
	i2c_host_fifo_fmt_empty	14.000s	1198.368us	1	1	100.00
	i2c_host_fifo_reset_rx	9.000s	694.058us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	188.000s	15884.577us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	13.000s	600.263us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	3.000s	88.190us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	903.068us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	2555.000s	52163.128us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	6.000s	1927.651us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	28.000s	4913.979us	1	1	100.00
	i2c_target_intr_smoke	9.000s	1427.285us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	189.073us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	211.766us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	28.000s	4913.979us	1	1	100.00
	i2c_target_intr_stress_wr	175.000s	4706.035us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	10.000s	987.993us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	310.000s	1226.793us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	7.000s	784.897us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	3.000s	1460.345us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	675.569us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	250.029us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	754.000s	3112.856us	1	1	100.00
	i2c_host_perf_precise	171.000s	1455.349us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	13.000s	600.263us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	66.349us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	6.000s	1947.346us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	561.423us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	235.732us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	20.000s	3691.643us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	5.000s	505.414us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	27.759us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	20.559us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	218.582us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	218.582us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	53.074us	1	1	100.00
	i2c_csr_rw	1.000s	80.693us	1	1	100.00
	i2c_csr_aliasing	2.000s	25.988us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	64.109us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	53.074us	1	1	100.00
	i2c_csr_rw	1.000s	80.693us	1	1	100.00
	i2c_csr_aliasing	2.000s	25.988us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	64.109us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	49.994us	1	1	100.00
	i2c_sec_cm	2.000s	129.477us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	49.994us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	6.000s	1180.108us	1
target_error_intr				1
	i2c_target_unexp_stop	4.000s	1392.252us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	13.000s	1846.946us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				2 test runs
	i2c_host_fifo_watermark	112032075364515771054808330662828441010239727777084678874189539344131425731723	None
	i2c_target_stress_wr	92691488878377689654117184891641101935557747857998004630489797419250186634858	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	33610446071658608401141089473358988013285947187126222860376305131313725923141	89	UVM_INFO @ 62776162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	96816722652341250395719276120535332381434984501903002833810283715446002154914	104	UVM_INFO @ 27394559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	79662000871337841454033826145521466777363318261898174966070967629924223760635	93	UVM_INFO @ 1180107632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	53477646533328969496575200403351964175788757970748220489213092763165606376495	96	UVM_INFO @ 1846946239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	7321047423110583967624155323031749454087198546177313545817810462223566339318	93	UVM_INFO @ 903067678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	27506049543795324549678381740828941650318637008348512894580961319324284277424	87	UVM_INFO @ 1392251621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	78799995407451308369215780589752760594870553732443905217821116576057982284009	96	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------