Simulation Results: lc_ctrl/volatile_unlock_disabled

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.20 %
  • code
  • 89.16 %
  • assert
  • 96.40 %
  • func
  • 79.03 %
  • block
  • 95.89 %
  • line
  • 96.66 %
  • branch
  • 89.54 %
  • toggle
  • 79.95 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
73.33%
V2S
70.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 24.558us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 19.615us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 235.084us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 118.600us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 48.992us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 3.000s 76.188us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 235.084us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 48.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 320.956us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 2904.526us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 13.643us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 261.461us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 8.000s 2932.329us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 8.000s 1945.984us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.000s 3021.607us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 710.060us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 284.223us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 690.036us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 555.890us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 331.680us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 74.260us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 79.938us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 8.000s 665.451us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 16.847us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.088s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 31.464us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 657.586us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 657.586us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 19.615us 1 1 100.00
lc_ctrl_csr_rw 2.000s 235.084us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 48.992us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 54.865us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 19.615us 1 1 100.00
lc_ctrl_csr_rw 2.000s 235.084us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 48.992us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 54.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 813.818us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 296.531us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 296.531us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 2904.526us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 813.818us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 813.818us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 813.818us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 813.818us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 813.818us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 813.818us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 813.818us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 813.818us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 261.461us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.000s 320.956us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 210.317us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 509.667us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 509.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
lc_ctrl_state_failure 74109159428601230131460731122039089808640057143312075693109471706451766102168 None
lc_ctrl_prog_failure 6004865566555647570370170060697867430554576521109262985387578219782483476153 None
lc_ctrl_errors 57089864623013721779047418690906145989600600787515347858967341683553161886470 None
lc_ctrl_jtag_state_failure 26115679720679551543930397779295086077331637798444946919071041554062022721454 None
lc_ctrl_jtag_state_post_trans 112281623349381239280617855885137227285022518632235501346170788013704217497189 None
lc_ctrl_jtag_prog_failure 15452595415908331246032052044594321932828195250448649666798907823400289218542 None
lc_ctrl_jtag_errors 24497827098490726342220324936825308146513366200279895347182570369475597112869 None
lc_ctrl_sec_mubi 12343375764655902141695731490760570990084066041388169641723521834924623871576 None
lc_ctrl_stress_all 68387486201375517031829334363187427144785532061064041392050922975430351296921 None
lc_ctrl_stress_all_with_rand_reset 33640777472417043138816471879443791543465782653913719296705775328917103352957 None