Simulation Results: lc_ctrl/volatile_unlock_enabled

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.99 %
  • code
  • 90.26 %
  • assert
  • 95.97 %
  • func
  • 77.74 %
  • block
  • 96.21 %
  • line
  • 96.91 %
  • branch
  • 90.39 %
  • toggle
  • 83.27 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
66.67%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 16.282us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 77.690us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.542us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 191.206us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.482us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 30.664us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 15.542us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 217.960us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 11.954us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 618.423us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 9 13 69.23
lc_ctrl_jtag_smoke 3.000s 255.643us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 9.000s 763.380us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.000s 1081.895us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 81.174us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 114.076us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 1058.182us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 115.542us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 28.860us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 396.990us 0 1 0.00
lc_ctrl_jtag_alert_test 2.000s 151.095us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 8.000s 3122.073us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 194.324us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.055s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 294.297us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 94.612us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 94.612us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 77.690us 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.542us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.482us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 45.540us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 77.690us 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.542us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.482us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 45.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 860.278us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 195.455us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 195.455us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 217.960us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 860.278us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 860.278us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 860.278us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 860.278us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 860.278us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 860.278us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 860.278us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 860.278us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 618.423us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 1045.458us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 416.491us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 416.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 93102353895318729397326824647418834010231347135362789381627603982763234578557 None
lc_ctrl_state_post_trans 87893455169463381405775055068002606737947319133142008540812693868075427728983 None
lc_ctrl_prog_failure 83305011234145304753297019529441539399480099456624590745074316698473685910578 None
lc_ctrl_errors 64310624827017854507622005601525713582694712279589262462816803632079016596963 None
lc_ctrl_jtag_state_failure 79941216472035226631849405130525588776397811152923633799128524499865849154918 None
lc_ctrl_jtag_state_post_trans 47560230823553536385766512458992330770180852450475666591058181679691790773685 None
lc_ctrl_jtag_prog_failure 9918905765203964687054269026020145910384472588774329430019487136813017178502 None
lc_ctrl_jtag_errors 48277291670110629358487952099369802331706254828808192967710102191391343448368 None
lc_ctrl_sec_mubi 14557209071399377647219857483844330637299646402950650079590345950187963139296 None
lc_ctrl_stress_all 31771391141967555537015659830440376139281223081296975305433536478523537057145 None
lc_ctrl_stress_all_with_rand_reset 72866159559049649215114162799581514221173958121687919753580900174290765899389 None
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 27794424387240986575498334704839290873737000861807457997621375428800445654640 160
UVM_INFO @ 396989926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---