Simulation Results: otp_ctrl

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.75 %
  • code
  • 72.59 %
  • assert
  • 93.99 %
  • func
  • 54.68 %
  • line
  • 87.49 %
  • branch
  • 84.12 %
  • cond
  • 86.03 %
  • toggle
  • 67.09 %
  • FSM
  • 38.23 %
Validation stages
V1
100.00%
V2
75.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.770s 234.616us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 11.850s 870.539us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 4.190s 400.656us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.600s 48.127us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.190s 603.866us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.080s 187.068us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.870s 225.821us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.600s 48.127us 1 1 100.00
otp_ctrl_csr_aliasing 4.080s 187.068us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.020s 161.729us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.270s 43.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 159.160s 7050.575us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.100s 131.000us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 14.830s 5247.550us 1 1 100.00
otp_ctrl_check_fail 9.600s 425.871us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 12.500s 1432.136us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 6.990s 307.025us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 26.770s 11142.984us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 17.590s 1307.605us 1 1 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 31.350s 2218.494us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.540s 640.268us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 6.300s 552.182us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 37.180s 10089.596us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.000s 81.880us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.190s 108.528us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.730s 447.286us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.730s 447.286us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.190s 400.656us 1 1 100.00
otp_ctrl_csr_rw 2.600s 48.127us 1 1 100.00
otp_ctrl_csr_aliasing 4.080s 187.068us 1 1 100.00
otp_ctrl_same_csr_outstanding 8.480s 2354.457us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 4.190s 400.656us 1 1 100.00
otp_ctrl_csr_rw 2.600s 48.127us 1 1 100.00
otp_ctrl_csr_aliasing 4.080s 187.068us 1 1 100.00
otp_ctrl_same_csr_outstanding 8.480s 2354.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
otp_ctrl_tl_intg_err 18.110s 830.546us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 18.110s 830.546us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 11.850s 870.539us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 11.850s 870.539us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
otp_ctrl_macro_errs 2.540s 640.268us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
otp_ctrl_macro_errs 2.540s 640.268us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 34.810s 668.405us 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.100s 131.000us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 9.600s 425.871us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 6.990s 307.025us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 6.990s 307.025us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 6.990s 307.025us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 6.990s 307.025us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 6.990s 307.025us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 11.850s 870.539us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 6.990s 307.025us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 11.850s 870.539us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 570.730s 73965.073us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 12.500s 1432.136us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 11.850s 870.539us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 11.850s 870.539us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.540s 640.268us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 113.290s 26644.223us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 48.090s 1273.779us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_check_fail 85666598417616044074449776841020177541495631806192235194796362528623485916372 4525
UVM_INFO @ 425870538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 49123735914293272365330744493170093034327739557037931653998892096377989810048 2568
UVM_INFO @ 552182212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 41627368324169066612837597749491932271902745202002585208169359131718928676284 17900
UVM_INFO @ 10089596417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 98105125594802759014794939137542306764153859251669782056937434201097033113387 112983
UVM_INFO @ 7050575119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 53183493078265600779496104923975978535491959158341450566299518428137375704439 95
UVM_INFO @ 26644223120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 53529552650896990112804358268141377347077088666339234243507543520027232103067 176
UVM_INFO @ 640267662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 38388147273452948919587708856406452948661283189926934678126558647231544765643 21593
UVM_INFO @ 1273778716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---