Simulation Results: rom_ctrl/32kb

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 92.75 %
  • code
  • 83.64 %
  • assert
  • 96.51 %
  • func
  • 98.10 %
  • block
  • 79.06 %
  • line
  • 79.28 %
  • branch
  • 80.93 %
  • toggle
  • 83.88 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 222.908us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 102.248us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 93.879us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 68.786us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 64.826us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 112.351us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 93.879us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 64.826us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 57.157us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 94.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 9.255us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 4.000s 266.700us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 4.000s 379.979us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 49.891us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 212.604us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 212.604us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 102.248us 1 1 100.00
rom_ctrl_csr_rw 2.000s 93.879us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 64.826us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 122.954us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 102.248us 1 1 100.00
rom_ctrl_csr_rw 2.000s 93.879us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 64.826us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 122.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 182.037us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 127.000s 876.765us 1 1 100.00
rom_ctrl_tl_intg_err 30.000s 177.812us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 127.000s 876.765us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 127.000s 876.765us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 127.000s 876.765us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 127.000s 876.765us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 222.908us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 222.908us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 222.908us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 30.000s 177.812us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 4.000s 379.979us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 182.037us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 127.000s 876.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 40.000s 11597.373us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 9369225245282893490585737875074859783782303419765178425569916926040075431522 88
UVM_INFO @ 9255128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_corrupt_sig_fatal_chk 41831536423510696513253202668871880003379148501240531756212653917130550446306 None